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mf1403-01 d e s i g n g u i d e standard cell S1K50000 series
notice no part of this material may be reproduced or duplicated in any from or by any means without the written permission of epson. epson reserves the right to make changes to this material without notice. epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this marerial will be free from any patent or copyright infringement of a third party. this material or portions there of may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ?seiko epson corporation 2001, all rights reserved.
new configuration of product number configuration of product number starting april 1, 2001 the configuration of product number descriprions will be changed as listed below. to order from april 1, 2001 please use these product numbers. for further information, please contact epson sales representative. devices s1 l 60843 f 00a0 packing specification specifications shape ( ? 2) model number model name ( ? 1) product classification (s1:semiconductor) 00 ? 1 : model name ? 2 : shape k standard cell l gate array x embedded array b assembled on board, cob, bga c plastic dip d bare chip f plastic qfp h ceramic dip l ceramic qfp m plastic sop r tab?fp t tape carrier (tab) 2 tsop (standard bent) 3 tsop (reverse bent)
contents standard cell S1K50000 series epson i design guide S1K50000 series table of contents chapter 1 overview.................................................................................................. 1 1.1 features.................................................................................................................. ...... 1 1.2 electrical characteristics............................................................................................... 2 1.3 outline of standard-cell development flow................................................................. 8 chapter 2 precautions on circuit design ............................................................ 10 2.1 insertion of input/output buffers ................................................................................. 10 2.2 use of differentiating circuits inhibited....................................................................... 10 2.3 wired logic inhibited .................................................................................................. 10 2.4 hazard protection ....................................................................................................... 11 2.5 fan-out limitations..................................................................................................... 11 2.6 internal bus circuits.................................................................................................... 1 2 2.7 bus hold circuits ........................................................................................................ 1 4 2.8 precautions on creating circuit diagrams (logic diagrams) ..................................... 15 2.9 clock tree synthesis .................................................................................................. 15 2.10 atpg (auto test-pattern generation)...................................................................... 19 2.11 limitations and restrictions on vhdl and verilog-hdl netlists .............................. 30 2.11.1 common ................................................................................................................. ......... 30 2.11.2 limitations and restrictions on verilog-hdl netlists....................................................... 31 2.11.3 limitations and restrictions on vhdl netlists................................................................. 32 chapter 3 types of input/output buffers and usage precautions.................... 33 3.1 types of input/output buffers ..................................................................................... 33 3.1.1 selecting input/output buffers .......................................................................................... .33 3.2 input/output-buffer configuration with a single power supply .................................. 35 3.2.1 input/output-buffer configuration with a single power supply ......................................... 35 3.2.1.1 input-buffer configuration with a single power supply............................................. 35 3.2.1.2 output-buffer configuration with a single power supply.......................................... 36 3.2.1.3 bidirectional-buffer configuration with a single power supply ................................. 39 3.2.2 fail-safe cells......................................................................................................... ........... 42 3.3 configuration of oscillator circuits.............................................................................. 47 3.3.1 when configuring an oscillator circuit .............................................................................. 47 3.3.2 precautions on the use of oscillator circuits..................................................................... 48 3.4 gated i/o cells ........................................................................................................... 49 3.4.1 outline of gated i/o cells .............................................................................................. .... 49 3.4.2 features of gated i/o cells ............................................................................................. .. 49 3.4.3 precautions on the use of gated i/o cells ........................................................................ 49 chapter 4 circuit design taking testability into account................................. 55 4.1 consideration for circuit initialization.......................................................................... 55 4.2 consideration for reduction of the test-pattern size................................................. 55 4.3 circuit configuration to facilitate dc and ac tests ................................................... 56 4.3.1 configuration of a test circuit ......................................................................................... .. 56 4.4 test circuit for functional cells .................................................................................. 62 4.4.1 configuration of a test circuit ......................................................................................... .. 62 4.4.2 test patterns........................................................................................................... ........... 62 4.4.3 test-circuit information................................................................................................ ...... 63 chapter 5 propagation delay time and timing design ..................................... 64 5.1 precautions regarding the relationship between ta and tj...................................... 64 5.2 simplified delay models.............................................................................................. 65 5.3 load due to input capacitance (load a).................................................................... 67 5.4 load due to wiring capacitance (load b) ................................................................. 68 5.5 calculating the propagation delay time..................................................................... 68
contents ii epson standard cell S1K50000 series design guide 5.6 calculating the output-buffer delay time ..................................................................70 5.7 flip-flop setup and hold times .................................................................................70 5.8 differentiating cell usage ...........................................................................................73 5.9 intra-chip skew ..........................................................................................................7 3 chapter 6 creating test patterns......................................................................... 74 6.1 testability consideration.............................................................................................74 6.2 usable waveform modulation.....................................................................................74 6.3 limitations on test patterns .......................................................................................75 6.3.1 test rate and the number of events ................................................................................ 75 6.3.2 input delay............................................................................................................. ............ 75 6.3.3 pulse width............................................................................................................. ........... 75 6.3.4 input-waveform format................................................................................................... .. 75 6.3.5 strobe .................................................................................................................. .............. 76 6.4 precautions regarding dc test .................................................................................76 6.5 precautions on use of an oscillator circuit ................................................................79 6.6 regarding the ac test ...............................................................................................80 6.6.1 restrictions on measurement events ................................................................................ 80 6.6.2 restrictions on ac test measurement points ................................................................... 80 6.6.3 restrictions on delays in the measured path.................................................................... 80 6.6.4 other restrictions ...................................................................................................... ........ 80 6.7 restrictions on test patterns for bidirectional pins ....................................................81 6.8 precautions on handling of the high-impedance state ..............................................81 chapter 7 estimating power consumption......................................................... 83 7.1 calculating power consumption.................................................................................83 7.2 limitations on power consumption ............................................................................87 chapter 8 pin arrangement and simultaneous operation ................................ 88 8.1 estimating the number of power-supply pins ............................................................88 8.2 simultaneously operating buffers and added power supply.....................................88 8.3 precautions on pin arrangement ................................................................................91 8.3.1 fixed power-supply pins................................................................................................. .. 91 8.3.2 precautions on pin arrangement....................................................................................... 91 8.3.3 example of the recommended pin arrangement ............................................................. 98 chapter 9 precautions on the use of dual power supplies ............................ 100 9.1 power-supply accommodation.................................................................................100 9.2 power supplies in a dual-power-supply system .....................................................101 9.3 dual-power-supply-type input/output buffers.........................................................101 9.3.1 lv dd -system input/output buffers .................................................................................. 102 9.3.1.1 lv dd -system input buffers ..................................................................................... 102 9.3.1.2 lv dd -system output buffers .................................................................................. 103 9.3.1.3 lv dd -system bidirectional buffers.......................................................................... 105 9.3.2 lv dd -system fail-safe cells........................................................................................... 107 9.3.3 hv dd -system input/output buffers ................................................................................. 109 9.3.3.1 hv dd -system input buffers..................................................................................... 109 9.3.3.2 hv dd -system output buffers.................................................................................. 111 9.3.3.3 hv dd -system bidirectional buffers ......................................................................... 114 9.3.4 hv dd -system fail-safe cells .......................................................................................... 117 9.4 calculating the delay time in a dual-power-supply system ...................................118 9.5 notes on calculating power consumption in a dual-power-supply system............119 9.6 estimating the number of power-supply pins in a dual-power-supply system ......121 appendix release note....................................................................................... 123
chapter 1: overview standard cell S1K50000 series epson 1 design guide chapter 1 overview seiko epsons S1K50000 series consists of high-function, high-integrated cmos standard cells based on the 0.35-micron process. 1.1 features ?high degree of integration maximum of 1,456,000 gates (2-input nand gate equivalents) ?operating speed internal gate: 136 ps (3.3 v typ.), 224 ps (2.0 v typ.) (2-input power nand, standard wiring load) input buffer: 380 ps (5.0 v typ.) using a level shifter, 400 ps (3.3 v typ.), 1.30 ns (2.0 v typ.) (standard wiring load) output buffer: 2.12 ns (5.0 v typ.) using a level shifter, 2.02 ns (3.3 v typ.), 3.90 ns (2.0 v typ.) (cl = 15 pf) ?process cmos 0.35-? al 3/4-layer metalization ?i/f level input/output ttl-, cmos-, and lvttl-compatible ?input mode ttl, cmos, lvttl, ttl schmitt, cmos schmitt, lvttl schmitt, and pci internal pull-up and pull-down resistors available (two resistance val- ues each) ?output mode normal, tri-state, bidirectional, or pci ?drive output i ol = 0.1 ma, 1 ma, 3 ma, 8 ma, 12 ma, or 24 ma selectable (when a 5.0-v level shifter is used) i ol = 0.1 ma, 1 ma, 2 ma, 6 ma, or 12 ma selectable (at 3.3 v) i ol = 0.05 ma, 0.3 ma, 0.6 ma, 2 ma, or 4 ma selectable (at 2.0 v) ?supports dual-power-supply operation using an internal level shifter (internal logic: low-voltage operation; input/output buffers: high- and low-voltage interfaces usable in combination) ?capable of operating with v dd = 2.0 v ?0.2 v
chapter 1: overview 2 epson standard cell S1K50000 series design guide 1.2 electrical characteristics *1: this applies to n-channel open-drain, bidirectional buffers, as well as xidc and xidh input buffers. for fail-safe cells, a value in the range from -0.3 v to 7.0 v is acceptable. *1: this applies to n-channel open-drain bidirectional buffers, as well as xlidc and xlidh or xhidc and xhidh input buffers. for fail-safe cells, a value in the range from -0.3 v to 7.0 v is acceptable. *2: this applies to buffers with an output current of 24 ma. *3: hv dd lv dd table 1-1 absolute maximum ratings (for a single power supply) parameter symbol rated value unit power-supply voltage v dd -0.3 to 4.0 v input voltage v i -0.3 to v dd + 0.5 *1 v output voltage v o -0.3 to v dd + 0.5 *1 v output current per pin i out ?30 ma storage temperature t stg -65 to 150 ? table 1-2 absolute maximum ratings (for dual power supplies) parameter symbol rated value unit power-supply voltage hv dd *3 -0.3 to 7.0 v lv dd *3 -0.3 to 4.0 v input voltage hv i -0.3 to hv dd + 0.5 *1 v lv i -0.3 to lv dd + 0.5 *1 v output voltage hv o -0.3 to hv dd + 0.5 *1 v lv o -0.3 to lv dd + 0.5 *1 v output current per pin i out ?30 ( ?50 *2 ) ma storage temperature t stg -65 to 150 ?
chapter 1: overview standard cell S1K50000 series epson 3 design guide *1: this applies to n-channel open-drain bidirectional buffers, as well as xidc and xidh input buffers. for fail-safe cells, a value of 5.25 v or 5.50 v is acceptable. *2: this temperature range refers to the recommended ambient temperature in cases where tj = 0 to 85 [?]. *3: this temperature range refers to the recommended ambient temperature in cases where tj = -40 to 125 [?]. *1: this applies to n-channel open-drain bidirectional buffers, as well as xidc and xidh input buffers. for fail-safe cells, a value of 5.25 v or 5.50 v is acceptable. *2: this temperature range refers to the recommended ambient temperature in cases where tj = 0 to 85 [?]. *3: this temperature range refers to the recommended ambient temperature in cases where tj = -40 to 125 [?]. table 1-3-1 recommended operating conditions (for a single power supply) parameter symbol min. ty p. max. unit power-supply voltage v dd 3.00 3.30 3.60 v input voltage v i v ss v dd *1 v ambient temperature ta 0 -40 25 25 70 *2 85 *3 ? normal input rising time t ri 50 ns normal input falling time t fa 50 ns schmitt input rising time t ri 5ms schmitt input falling time t fa 5ms table 1-3-2 recommended operating conditions (for a single power supply) parameter symbol min. ty p. max. unit power-supply voltage v dd 1.80 2.00 2.20 v input voltage v i v ss v dd *1 v ambient temperature ta 0 -40 25 25 70 *2 85 *3 ? normal input rising time t ri 100 ns normal input falling time t fa 100 ns schmitt input rising time t ri 10 ms schmitt input falling time t fa 10 ms
chapter 1: overview 4 epson standard cell S1K50000 series design guide *1: this applies to n-channel open-drain bidirectional buffers, as well as xlidc and xlidh input buffers. for fail- safe cells, a value of 5.25 v or 5.50 v is acceptable. *2: this temperature range refers to the recommended ambient temperature in cases where tj = 0 to 85 [?]. *3: this temperature range refers to the recommended ambient temperature in cases where tj = -40 to 125 [?]. *1: this applies to n-channel open-drain bidirectional buffers, as well as xlidc and xlidh or xhidc and xhidh input buffers. for fail-safe cells, a value of 5.25 v or 5.50 v is acceptable. *2: this temperature range refers to the recommended ambient temperature in cases where tj = 0 to 85 [?]. *3: this temperature range refers to the recommended ambient temperature in cases where tj = -40 to 125 [?]. table 1-4-1 recommended operating conditions (for dual power supplies) parameter symbol min. ty p. max. unit power-supply voltage (high voltage) hv dd 4.75 4.50 5.00 5.00 5.25 5.50 v power-supply voltage (low voltage) lv dd 3.00 3.30 3.60 v input voltage hv i v ss hv dd v lv i v ss lv dd *1 ambient temperature ta 0 -40 25 25 70 *2 85 *3 ? normal input rising time t ri 50 ns normal input falling time t fa 50 ns schmitt input rising time t ri 5ms schmitt input falling time t fa 5ms table 1-4-2 recommended operating conditions (for dual power supplies) parameter symbol min. ty p. max. unit power-supply voltage (high voltage) hv dd 3.00 3.30 3.60 v power-supply voltage (low voltage) lv dd 1.80 2.00 2.20 v input voltage hv i v ss hv dd *1 v lv i v ss lv dd *1 ambient temperature ta 0 -40 25 25 70 *2 85 *3 ? normal input rising time ht ri 50 ns lt ri 100 normal input falling time ht fa 50 ns lt fa 100 schmitt input rising time ht ri 5 ms lt ri 10 schmitt input falling time ht fa 5 ms lt fa 10
chapter 1: overview standard cell S1K50000 series epson 5 design guide *1: the values in ( ) apply to cases where ta = 0? to 70?. *2: conforms to pci standard rev. 2.2 table 1-5 electrical characteristics (hv dd = 5 v common; v ss = 0 v; ta = -40? to 85?) parameter symbol test conditions min. ty p. max. unit input leakage current i li ?11a off-state leakage current i oz ?11a high-level output voltage v oh i oh = -0.1 ma (type s), -1 ma (type m) -3 ma (type 1), -8 ma (type 2) -12 ma (type 3, type 4) hv dd = min. hv dd -0.4 v low-level output voltage v ol i ol = 0.1 ma (type s), 1 ma (type m) 3 ma (type 1), 8 ma (type 2) 12 ma (type 3), 24 ma (type 4) hv dd = min. 0.4 v high-level input voltage v ih1 cmos level, hv dd = max. 3.5 v low-level input voltage v il1 cmos level, hv dd = min. 1.0 v positive trigger voltage v t1+ cmos schmitt 2.0 4.0 v negative trigger voltage v t1- cmos schmitt 0.8 3.1 v hysteresis voltage v h1 cmos schmitt 0.3 v high-level input voltage v ih2 ttl level, hv dd = max. 2.0 v low-level input voltage v il2 ttl level, hv dd = min. 0.8 v positive trigger voltage v t2+ ttl schmitt 1.2 2.4 v negative trigger voltage v t2- ttl schmitt 0.6 1.8 v hysteresis voltage v h2 ttl schmitt 0.1 v high-level input voltage *2 v ih3 pci level, hv dd = max. 2.0 v low-level input voltage *2 v il3 pci level, hv dd = min. 0.8 v high-level output voltage *2 i oh3 for pci, v oh = 1.4 v, hv dd = min. v oh = 3.1 v, hv dd = max. -44 -142 ma ma low-level output voltage *2 i ol3 for pci, v ol = 2.20 v, hv dd = min. v ol = 0.71 v, hv dd = max. 95 206 ma ma pull-up resistance *1 r pu v i = 0 v type 1 30 60 (120) 144 k ? type 2 60 120 (240) 288 pull-down resistance *1 r pd v i = v dd type 1 30 60 (120) 144 k ? type 2 60 120 (240) 288 high-level hold current i bhh for bus hold, v in = 2.0 v hv dd = min. -80 ? low-level hold current i bhl for bus hold, v in = 0.8 v hv dd = min. 33 ? high-level reversing current i bhho for bus hold, v in = 0.8 v hv dd = max. -550 ? low-level reversing current i bhlo for bus hold, v in = 2.0 v hv dd = max. 330 ? input-pin capacitance c i f = 1 mhz, hv dd = 0 v 10 pf output-pin capacitance c o f = 1 mhz, hv dd = 0 v 10 pf input/output-pin capacitance c io f = 1 mhz, hv dd = 0 v 10 pf
chapter 1: overview 6 epson standard cell S1K50000 series design guide *1: the quiescent current represents the typical value for each series at tj = 85?. for details, see tables 1-8 through 1-9. *2: the values in ( ) apply to cases where ta = 0? to 70?. for cases where hv dd = 3.3 v + 0.3 v; v ss = 0 v; ta = -40? to 85?, each value should be doubled. *3: conforms to pci standard rev. 2.2 table 1-6 electrical characteristics (v dd = lv dd = 3.3 v ?0.3 v, vss = 0 v, ta = -40 to 85?) parameter symbol test conditions min. ty p. max. unit quiescent current *1 i dds static state 170 ? input leakage current i li ?11a off-state leakage current i oz ?11a high-level output voltage v oh i oh = -0.1 ma (type s), -1 ma (type m) -2 ma (type 1), -6 ma (type 2) -12 ma (type 3) v dd = min. v dd -0.4 v low-level output voltage v ol i ol = 0.1 ma (type s), 1 ma (type m) 2 ma (type 1), 6 ma (type 2) 12 ma (type 3) v dd = min. 0.4 v high-level input voltage v ih1 lvttl level, v dd = max. 2.0 v low-level input voltage v il1 lvttl level, v dd = min. 0.8 v positive trigger voltage v t1+ lvttl schmitt 1.1 2.4 v negative trigger voltage v t1- lvttl schmitt 0.6 1.8 v hysteresis voltage v h1 lvttl schmitt 0.1 v high-level input voltage *3 v ih3 pci level, v dd = max. 1.71 v low-level input voltage *3 v il3 pci level, v dd = min. 0.98 v high-level output voltage *3 i oh3 for pci, v oh = 0.90 v, v dd = min. v oh = 2.52 v, v dd = max. -36 -115 ma low-level output voltage *3 i ol3 for pci, v ol = 1.80 v, v dd = min. v ol = 0.65 v, v dd = max. 48 137 ma pull-up resistance *2 r pu v i = 0 v type 1 20 50 (100) 120 k ? type 2 40 100 (200) 240 pull-down resistance *2 r pd v i = v dd type 1 20 50 (100) 120 k ? type 2 40 100 (200) 240 high-level hold current i bhh for bus hold, v in = 2.0 v v dd = min. -20 ? low-level hold current i bhl for bus hold, v in = 0.8 v v dd = min. 17 ? high-level reversing current i bhho for bus hold, v in = 0.8 v v dd = max. -350 ? low-level reversing current i bhlo for bus hold, v in = 2.0 v v dd = max. 210 ? input-pin capacitance c i f = 1 mhz, v dd = 0 v 10 pf output-pin capacitance c o f = 1 mhz, v dd = 0 v 10 pf input/output-pin capacitance c io f = 1 mhz, v dd = 0 v 10 pf
chapter 1: overview standard cell S1K50000 series epson 7 design guide *1: the quiescent current represents the typical value for each series at tj = 85?. for details, see tables 1-8 through 1-9. table 1-7 electrical characteristics (v dd = lv dd = 2.0 v ?0.2 v, vss = 0 v, ta = -40 to 85?) parameter symbol test conditions min. ty p. max. unit quiescent current *1 i dds static state 150 ? input leakage current i li ?11a off-state leakage current i oz ?11a high-level output voltage v oh i oh = -0.05 ma (type s), -0.3 ma (type m) -0.6 ma (type 1), -2 ma (type 2) -4 ma (type 3) v dd = min. v dd -0.2 v low-level output voltage v ol i ol = 0.05 ma (type s), 0.3 ma (type m) 0.6 ma (type 1), 2 ma (type 2) 4 ma (type 3) v dd = min. 0.2 v high-level input voltage v ih1 cmos level, v dd = max. 1.6 v low-level input voltage v il1 cmos level, v dd = min. 0.3 v positive trigger voltage v t1+ cmos schmitt 0.4 1.6 v negative trigger voltage v t1- cmos schmitt 0.3 1.4 v hysteresis voltage v h1 cmos schmitt 0 v pull-up resistance r pu v i = 0 v type 1 30 120 300 k ? type 2 60 240 600 pull-down resistance r pd v i = v dd type 1 30 120 300 k ? type 2 60 240 600 high-level hold current i bhh for bus hold, v in = 1.6 v v dd = min. -2 ? low-level hold current i bhl for bus hold, v in = 0.3 v v dd = min. 2a high-level reversing current i bhho for bus hold, v in = 0.3 v v dd = max. -100 ? low-level reversing current i bhlo for bus hold, v in = 1.6 v v dd = max. 100 ? input-pin capacitance c i f = 1 mhz, v dd = 0 v 10 pf output-pin capacitance c o f = 1 mhz, v dd = 0 v 10 pf input/output-pin capacitance c io f = 1 mhz, v dd = 0 v 10 pf
chapter 1: overview 8 epson standard cell S1K50000 series design guide *1: varies with the chip size and incorporated macro hi dds : quiescent current between hv dd and v ss ; li dds : quiescent current between lv dd and v ss *1: varies with the chip size and incorporated macro for the quiescent current in cases where tj = 85?, an approximate value can be obtained using the equation below (tj = -40? to 85?, however). i dd (tj) = i dds (tj = 85?) temperature coef?ient = i dds (tj = 85?) 10 (for cases where tj = 125?, calculate the above using temperature coef?ient = 12.) for dual power supplies, the sum of quiescent currents for the respective voltages used comprises a total quiescent current. (hi dds + li dds ) 1.3 outline of standard-cell development flow the standard cells were developed through collaboration between seiko epson and its customers. customers perform a range of work, from system and circuit designs to test- pattern design, using the cell libraries and various design materials offered by seiko epson. for interfacing information, customers are expected to conduct preliminary checks based on the data-release checklist included in the appendix herein, and present the necessary data and documentation to seiko epson. customers are responsible for conducting simulations using the eda software or auklet* on hand; the remainder of the work, beginning with placement and routing, is undertaken by seiko epson. note) *1 : auklet is seiko epson? asic design support system and can be run on ms windows 95/98/nt. the following eda software can currently be simulated: ?verilog-xl (*1) ? vss (*2) ?modelsim (*3) note) *1 : verilog-xl is a registered trademark of cadence design systems of the u.s. note) *2 : vss is a registered trademark of synopsys of the u.s. note) *3 : modelsim is a registered trademark of model technology of the u.s. for details, please contact seiko epson or its distributor. table 1-8 quiescent current (for a single power supply) (tj = 85?) parameter 3.3 v ?0.3 v i dds max. 2.0 v ?0.2 v i dds max. unit quiescent current *1 35 to 260 31 to 230 ? table 1-9 quiescent current (for dual power supplies) (tj = 85?) parameter 5 v ?10% hi dds max. 3.3 v ?0.3 v li dds max. 3.3 v ?0.3 v hi dds max. 2.0 v ?0.2 v li dds max. unit quiescent current *1 30 to 80 35 to 260 25 to 60 31 to 230 ? tj - 85 60
chapter 1: overview standard cell S1K50000 series epson 9 design guide the diagram below shows the ?w of the standard cell development procedure. customer agent (interface) seiko epson product planning functional specification circuit design test-pattern design logic verification (simulation) timing verification (simulation) (final simulation) mask production ts (test sample) production mass-production establishment mass production delivery- specification issuance simulation file simulation list es (ts) prototype- evaluation approval notification delivery specification delivery- specification approval notification wiring diagram pin arrangement table ?timing waveform diagram ?marking diagram specification order sheet ng delay-time analysis delay-time analysis ok ng ng ok ng ng ok ok es (ts) approval notification delivery- specification approval () () () () () () those tasks enclosed in ( ) are undertaken when requested by the customer. es (engineering sample) production logic specification confirmation specification approval overall evaluation functional evaluation confirmation confirmation development commencement request automatic placement & routing confirmation
chapter 2: precautions on circuit design 10 epson standard cell S1K50000 series design guide chapter 2 precautions on circuit design 2.1 insertion of input/output buffers in the design of your circuit, always be sure to use input/output buffers to exchange signals with external devices. because cmos ics are extremely susceptible to damage by static electricity, the input/output buffers contain protective circuits. 2.2 use of differentiating circuits inhibited in lsis, the tpd of each gate varies depending on the process dispersions during mass production or the operating environment. therefore, differentiating circuits using the relative time difference of tpd like the one shown in figure 2-1 cannot obtain a suf?ient pulse width, causing the circuit to operate erratically. when it is necessary to use a differentiating circuit, be sure to use one that utilizes ?p-?ps, rather than the one shown in figure 2-1. figure 2-1 example of a differentiating circuit 2.3 wired logic inhibited because cmos transistors are used, wired logic cannot be con?ured as in bipolar transistors. therefore, the output pins of cells cannot be connected together, as shown in figure 2-2. output pins can only be connected together in a bus-circuit con?uration. figure 2-2 example of inhibited wired logic
chapter 2: precautions on circuit design standard cell S1K50000 series epson 11 design guide 2.4 hazard protection in circuits or decoders con?ured by combining gates such as nand or nor gates, a very short pulse may be generated due to the difference in delay times between gates. this short pulse is known as a hazard, and it causes malfunction when fed into the clock or reset pins of ?p-?ps. therefore, circuits where such a hazard is likely to occur must be con?ured so as to prevent the hazard from propagating. for decoders, it may be necessary to use a circuit that has an enable pin. 2.5 fan-out limitations the tpd of logic gates is determined by the load capacitance of their output pin. an excessively large load capacitance may not only cause the tpd to become large, but may also cause malfunction. therefore, there are limitations on the number of loads that can be connected to the output pins of each logic gate. these are known as ?an-out limitations. the input-pin capacitance of each logic gate, however, tends to differ depending on the logic- gate input. the input capacitance of each logic gate, in terms of the input capacitance of an inverter (kini) = 1, is known as ?an-in. in the design of your circuit, make sure the total number of fan-ins connected to the output pins of each logic gate does not exceed the fan-out limitations of those output pins. furthermore, for logic gates operating at high speed, such as high-speed clock lines (fmax = 40 mhz or more), make sure the output-pin capacitance of those gates is approximately half the fan-out limitation.
chapter 2: precautions on circuit design 12 epson standard cell S1K50000 series design guide 2.6 internal bus circuits a bus circuit is con?ured with 3-state logic circuits, so one of the outputs connected to the bus can be driven active (while the other outputs are placed in the high-impedance state) by turning the bus control signals on or off. in this way, a transmission-signal line on the bus is shared by dividing it in time. although bus circuits are very effective for logic design, note the following when using a bus circuit. precautions on the use of bus circuits (1) bus cells can only be used for bus circuits (for the S1K50000-series bus cells, see table 2-1). (2) when using bus cells, add bus de?ition cells kblt to the bus in the con?uration of your circuit. (3) up to 32 bus cells can be connected to one length of bus. (4) of the bus cells connected to one length of bus, only one output can be active (0 or 1) at one time, and all other bus cell outputs must be placed in the high-impedance state (z). (5) even when all of the bus cells connected to one length of bus are in the high-impedance state (z), data may be retained by a bus latch cell. however, the retained data should be left ?ating, and should not be used as logic signals. (6) in the creation of your test pattern, make sure the bus initial state will settle easily, to ensure improved testability. in addition, add one or more test pins to make the bus easily controllable. (7) the bus control signals within the same event rate can be switched only once. (8) excessive fan-out of the bus circuit may cause the propagation delay time to increase, making high-speed operation dif?ult.
chapter 2: precautions on circuit design standard cell S1K50000 series epson 13 design guide the usable bus cells in the S1K50000 series are listed in table 2-1. figure 2-3 typical configuration of a bus cell circuit table 2-1 S1K50000-series bus cells cell type cell name 1 bit 4 bit 8 bit bus latches kblt 1 kblt 4 kblt 8 bus driver ktsb, ktsb4, ktsb8, ktsbp kt244h kt244 inverting bus driver ktsv, ktsv4, ktsv8, ktsvp kt240h kt240 transparent latches with reset and 3-state output kt373h kt373 d-?p ?ps with rest and 3-state output kt374h kt374 1-bit ram krm1 kblt ktsb ktsb kin 1 kna 2
chapter 2: precautions on circuit design 14 epson standard cell S1K50000 series design guide 2.7 bus hold circuits available with the S1K50000 series are input/output buffers with a bus hold function to hold the input/output-pin data in order to prevent the output pins or bidirectional pins from entering a high-impedance state. however, because the retention capability of the bus hold circuit is repressed so as not to adversely affect normal bus operation, do not use the retained output as valid data. if any data is fed from an external device, the state of the data may change easily. for details on the bus hold circuits output retention current, see tables 1-5 through 1-7. figure 2-4 typical bus hold circuit symbol xtb1ht a e ta used for testing output signal output te ts enable used for testing output signal enable (a) output buffer (b) bidirectional buffer xbc1ht a e ta bidirectional te ts input signal
chapter 2: precautions on circuit design standard cell S1K50000 series epson 15 design guide 2.8 precautions on creating circuit diagrams (logic diagrams) for diagram interfaces, circuit diagrams are normlly presented to seiko epson by the customer. in the creation of your circuit diagrams, note the following: for the seiko epson format, use the logic symbols listed in ?tandard cell S1K50000-series msi cell library. do not use the aslant wiring shown in the circuit diagram. to write input/output and bidirectional pin names, use 2 to 32 alphanumeric characters beginning with an english letter. 2.9 clock tree synthesis (1) outline clock tree synthesis is a service that automatically inserts a tree of a set of buffers with optimized clock line skew and delay. in some cases, clock trees are inserted by the customers themselves for the purpose of clock line fan-out adjustment or the like. however, because in such a case trees are automatically placed and routed by p&r tools, the clock line may, in effect, have an increased clock skew. in addition, wiring delay may eventually be increased to a greater extent than predicted, as placement & routing and cell delays are often imbalanced. clock tree synthesis solves all of these problems ef?iently. (2) method of practice before a clock tree can be automatically inserted, the clock line must have a dedicated buffer inserted by the customer for the following three purposes: determination of the location at which to apply clock tree synthesis performance of a preliminary routing-level simulation (pre-simulation) through estimation of the delay in the inserted clock tree back annotation of the delay in the inserted clock tree to allow the performance of precise post-simulation choose the dedicated buffer for clock tree synthesis from the table of dedicated buffers provided later. when inserting the selected dedicated buffer, handle it the same way as with ordinary cells by referring to the ?mage diagram, in consideration of the ?estrictions and precautions. in addition, for logic-synthesis-based design, because the dedicated buffer cannot be automatically inserted, write the procedure using description language directly. at that time, execute the command speci?d below to ensure that another buffer will not be synthesized on the clock line in which the dedicated buffer has been inserted: set_dont_touch_net net_name
chapter 2: precautions on circuit design 16 epson standard cell S1K50000 series design guide [dedicated buffers] choose the dedicated buffer from among those listed below, in accordance with the fan-out. note 1: the k value of these cells (delay due to fan-out) is set to 0 in pre-simulation. note 2: the fan-out counts for these cells are set to infinity. note 3: the delay relative to the fan-out counts is only an approximate value for use as a guideline. [restrictions and precautions] applicable series: s1l9000f, s1l30000, s1l35000, s1l50000, S1K50000 the dedicated buffers can only be used for the purpose of clock tree synthesis. clock tree synthesis can also be applied to data lines or other control signals. however, if the number of nets to which clock tree synthesis is applied increases, a large skew or delay may result. therefore, limit the number of synthesized nets to 10, and limit the application of synthesis to critical nets with a large fan-out. the application of clock tree synthesis to nets with a small fan-out may result in increased delay or skew. apply synthesis only to nets that have a fan-out of several tens or more. clock tree synthesis may also help to adjust the skew between multiple clock lines. in such a case, consult seiko epson after presenting a detailed block diagram (clearly showing the clock-line structure). for a set of clock lines that have the same clock root and are divided into multiple clock lines by gates or the like, ?ated clock-tree synthesis explanation data is separately required. in such a case, contact seiko epson. S1K50000 series cell name to max. (ns) approximate fan-out count kcrbf2 2.00 0 to 500 kcrbf3 3.00 500 to 3000 kcrbf4 4.00 3000 to 10000 kcrbf5 5.00 over 10000 kcrbf6 6.00 kcrbf7 7.00 kcrbf8 8.00
chapter 2: precautions on circuit design standard cell S1K50000 series epson 17 design guide [required information] to ensure the ef?ient use of clock tree synthesis, please send the information speci?d below to seiko epson by the time data is released. note 1: the target values are only approximate for use as guidelines in the application of synthesis, and it is not guaranteed that the values will be satisfied. note 2: if you do not have definite target values, specify your desired values by entering a comment (e.g., ?s small as possible?. instance name of kcrbf* target skew value target delay value (min./max.)
chapter 2: precautions on circuit design 18 epson standard cell S1K50000 series design guide [image diagram] shown below is an example of a logic-circuit diagram to be presented by the customer and a layout-circuit diagram derived from it through the application of clock tree synthesis at seiko epson. figure 2-6 layout diagram derived by applying clock tree synthesis at seiko epson clock root clock tree synthesis back annotation of delay kcrbf* figure 2-5 customer? logic circuit
chapter 2: precautions on circuit design standard cell S1K50000 series epson 19 design guide 2.10 atpg (auto test-pattern generation) (1) introduction atpg refers to automatic pattern generation, for which tools are released from each tool vendor. testgen from synopsys is used for asic design by seiko epson. use of testgen helps to automatically generate a test pattern following the insertion of scan circuits into the original circuit. the word ?ontrol as used in this manual means that any level can be applied to the target pin without being routed via a sequential circuit. that is, it does not refer to clocks, such as divided-by-n clocks, that require several cycles for status settings. for example, the description, ?ach ?p-?p can have its clock controlled from the outside refers to a circuit in which an external input clock (clocking source) can reach each ?p-?p. (2) outline scan insertion is executed on circuits that conform to the design rules required for atpg support, and fault detection by atpg is performed. in addition, because atpg tools operate the internal nodes forcibly from external pins through a scan circuit, the test patterns output by atpg tools cannot be used to observe operation of the user circuit. therefore, customers are requested to create the test pattern necessary to verify the basic operation of the circuit. in other words, keep in mind that the test patterns generated by atpg tools are used only for the purpose of increasing the fault detection rate. the use of atpg tools helps to generate a test pattern that, for full-scan circuits, can attain a high fault detection rate of close to 100%, except for untestable nodes in which logical fault detection is impossible. note that atpg uses the full-scan method based on muxscan-type ?p- ?ps.
chapter 2: precautions on circuit design 20 epson standard cell S1K50000 series design guide (3) de?ition of the fault detection rate the single-degeneracy fault mode is used. sa0: fixed (shorted) to 0 sa1: fixed (shorted) to 1 the atpg tool (testgen) generates the test pattern shown below. a test pattern is generated in such a way that sa1 and sa0 are set for each node and that, when they are ?ed to the observable logic level of 0 or 1, a functional failure results. figure 2-7 example of an untestable fault s-a-1 s-a-0/1 kor2 kin1 d c kdf s-a-0 kad2 q xq d c kdf q xq
chapter 2: precautions on circuit design standard cell S1K50000 series epson 21 design guide (4) design ?w (1/2) figure 2-8 atpg flow for development by auklet atpg rule check seiko epson customers atpg application notes preliminary netlist atpg check sheet tentative pin arrangement table circuit block diagram examination result content confirmation input pattern expected value netlist circuit data netlist circuit data pin layout table atpg auklet drawing registration tp generation auklet atpg rule check pre-simulation atpg rule check atpg rule check scan insertion fault detection post-atpg check fault-detection rate confirmation ok or ng p & r p & r clock tree synthesis post-simulation post-simulation result post-simulation result confirmation sign-off
chapter 2: precautions on circuit design 22 epson standard cell S1K50000 series design guide (4) design ?w (2/2) figure 2-9 atpg flow for development by logic synthesis atpg pre-simulation ok or ng p & r p & r clock tree synthesis post-simulation atpg rule check seiko epson customers atpg application notes preliminary netlist atpg check sheet tentative pin arrangement table circuit block diagram examination result content confirmation input pattern expected value netlist circuit data netlist circuit data pin layout table tp generation atpg rule check logic synthesis atpg rule check atpg rule check scan insertion fault-detection rate detection post-atpg check verilog-xl fault-detection rate confirmation post-simulation result post-simulation result confirmation sign-off language design rtl generation
chapter 2: precautions on circuit design standard cell S1K50000 series epson 23 design guide (5) con?uration of test patterns generated by atpg the test patterns generated by atpg have the two modes speci?d below, and these two modes must be switched over using a scan enable input pin (scanen). because the scanen pin is connected for circuit scanning, make sure your circuits have this pin prepared as a dedicated input pin. scan shift mode in this mode, data is input and output to and from the circuits internal storage device (?p- ?p) con?ured as a shift register. scan test mode in this mode, the data applied to the storage device in scan shift mode is operated internally through the entry of a clock. (6) input/output pins for atpg the pins needed for atpg are described below. of these, the provision of two pins, scanen and atpgen, is suf?ient for atpg to be run ef?iently. this may result in a reduced delivery period and an increased fault detection rate, however. scan enable input pin (scanen) this pin is used to switch between scan-shift and scan-test modes. it also is used to reset or set the ?p-?p, and to ? the bidirectional input/output select signal during scan shift. because this pin is always necessary for scanning, be sure to prepare it as a dedicated input pin. atpg test input pin (atpgen) this pin makes the circuit suitable for atpg, and is used to ? the circuits internal asynchronous parts or for switchover to make clock lines controllable that cannot be controlled from the outside. this pin is unnecessary if the atpg rules were taken into consideration in the design of the original circuit. prepare this pin as a dedicated input pin. scan data input pin this input pin is used to set data in the shift register generated by scanning. two or more of these pins may exist, depending on the number of scan ?p-?ps, and this pin may be shared with other pins. however, it cannot be shared with the control pins that reset/set the clock, nor can it be shared with other pins employed for scanning. if it is shared with bidirectional pins, make sure the pin is always in input state through the use of the atpgen pin, for example. scan data output pin this pin is used to read data from the shift register generated by scanning. two or more of these pins may exist, depending on the number of scan ?p-?ps, and this pin may be shared with other pins. however, if it is shared with bidirectional pins, make sure the pin is always in output state through the use of the atpgen pin, for example.
chapter 2: precautions on circuit design 24 epson standard cell S1K50000 series design guide scan clock input pin this clock input pin is in the test pattern generated by atpg. in most cases, this pin uses the system clock during normal operation. (7) logic circuit design rules for atpg support (dft) in order for atpg to be performed, the logic circuit is scanned. in the creation of the original circuit, be sure to follow the rules speci?d below to ensure that it will have good observability. practical examples are shown below. if these measures are dif?ult to implement or there are any uncertainties about them, contact seiko epson. applicable series: s1l50000, s1l30000, s1l9000f, s1x50000, S1K50000 prepare one scan enable input pin (scanen) as a dedicated input pin. submit ?rial data to seiko epson one week prior to the release of the formal data. this trial data is necessary to preliminarily check your circuit prior to formal data-in, in order to increase the ef?iency of work following formal data-in and achieve a high fault detection rate. the clock, reset, and set inputs of all ?p-?ps to be scanned must be controllable directly from the external pins. ? if not controllable, con?ure a controllable circuit by attaching an atpg test input pin (atpgen) separately from the scanen pin. ? if the ?p-?ps are con?ured to have multiple clocks fed from external pins, make sure all of the ?p-?ps to be scanned basically operate with a single clock input when atpgen is active. however, if two or more of such circuit con?urations exist, consult seiko epson. figure 2-10 example of processing of the clock line circuit design using scan ?p-?ps in the original circuit is inhibited. skew consideration for clock nets by clock tree synthesis must be supported. i/o cells must be placed on the top hierarchical level. clk xibc xibcd1 atpgen logic kao24a kcrbf* dq cxq kdf dq cxq kdf
chapter 2: precautions on circuit design standard cell S1K50000 series epson 25 design guide do not use internal tri-state buses. ? correct the circuit to con?ure internal tri-state buses with multiplexers or the like. if it is unavoidable to use internal tri-state buses, use the atpgen pin to ensure that those bus circuits will not contend for bus control. however, because this measure is detrimental to increasing the fault detection rate, do not use such a circuit con?uration if a high fault detection rate is desired. figure 2-11 example of the processing of internal tri-state buses when using macro cells such as ram, rom, or megacells, include the ?p-?ps to be scanned in your circuit con?uration before and after the input/output ports of those macro cells. ? without such a circuit con?uration, fault detection before and after the macro cells may not be guaranteed. avoid the use of msi macros that include ?p-?ps (e.g., kt175 or ka161). ? msi cells are not scanned. if a high fault detection rate is desired, do not use msi cells. the use of circuits that tend to cause racing, such as rs latches and differentiating cir- cuits, as well as the use of asynchronous circuits, are inhibited. ? when using such circuits, be sure to ? the circuit outputs with the atpgen pin. however, because this measure is detrimental to increasing the fault detection rate, do not use these circuits if a high fault detection rate is desired. fix the latch cells with the atpgen pin to ensure that they will always be in a through state. ? because this measure is detrimental to increasing the fault detection rate, avoid using latch cells whenever possible if a high fault detection rate is desired. make sure the bidirectional pins are set for input during scan shift mode. ? if it is unavoidable for the bidirectional pins to be assigned for scan data input or scan data output, ? the pins for input or output, respectively. xibcd1 atpgen z1 kblt1 ktsb ktsb
chapter 2: precautions on circuit design 26 epson standard cell S1K50000 series design guide figure 2-12 example of the processing of bidirectional pins fix the outputs of non-scanned ?p-?ps. ? the outputs of msi macros that include t-?p-?ps or ?p-?ps, as well as those of non-scanned ?p-?ps, cause malfunction in the atpg test pattern or hinder fault detection. therefore, ? their outputs using the atpgen pin as much a as possible. (8) other depending on the number of scanned ?p-?ps, the number of gates increases by approximately 15% to 20% compared to that in the original circuit. the period required for dft and atpg depends on the circuit con?uration and gate size. the dft and atpg work at seiko epson requires at least three days, which should be taken into account in your plan. (in some cases, depending on the circuit con?ura- tion, approximately 10 days may be required. therefore, please carefully examine the presented materials when designing your circuit.) prior to data-in, please send the ?tpg check sheet and ?xternal pin information to seiko epson. if circuit changes are required, you will be requested to make them. the test pattern interfaced to seiko epson should include de?itions of the external pins (e.g., atpgen and scanen) for scan purposes. for atpg support, cts (clock tree synthesis) is essential during placement and routing. therefore, please submit the necessary information for clock tree synthesis speci?d on page 15, along with said information. xibcd1 atpgen xibcd1 xbc1 xbc1 xbc1 a e a e a e d1 d0 d2 scanout scanin scanen
chapter 2: precautions on circuit design standard cell S1K50000 series epson 27 design guide (9) atpg check sheet please be sure to submit this sheet one week prior to data-in. encircle the appropriate answer for each question. 1. interface netlist format for seiko epson (gate level) verilog or edif 2. are scan ?p-?ps used in the original circuit? (note 1) yes or no 3. is any macro cell, msi cell, or intermittently oscillating cell used? yes or no 4. if yes, enter the cell name: ____________________________________________ 5. is any internal tri-state bus used? yes or no 6. does any rs latch, differentiating circuit, or asynchronous circuit exist? yes or no 7. are latch cells used? yes or no 8. are bidirectional pins included? yes or no 9. is there any clock that cannot be controlled directly from the outside? yes or no 10. are there any reset/set pins for ?p-?ps or latch cells that cannot be controlled directly from the outside? yes or no 11. if you answered yes to any of questions 3 through 10 above, is your circuit designed in conformity with the dft rules? (note 2) y es or no 12. are i/o cells placed at the top level? y es or no 13. are measures taken to correct the skew problems of clock nets by clock tree synthesis? y es or no note 1: if yes, please correct your circuit, as the circuit cannot be scanned. note 2: if no, please insert dft, as the circuit cannot be scanned. in addition, if you would like to request dft insertion by seiko epson because detailed circuit information is required in addition to this sheet, contact seiko epson.
chapter 2: precautions on circuit design 28 epson standard cell S1K50000 series design guide ?external pin information enter the names of pins that match those in the pin arrangement table. the necessary pins vary with the circuit con?uration. (always be sure to specify the necessary pins.) ?clock input pins pin name:______________ active edge: rise ? fall pin name:______________ active edge: rise ? fall pin name:______________ active edge: rise ? fall pin name:______________ active edge: rise ? fall pin name:______________ active edge: rise ? fall ?scan enable input pin (note 3) .................................................. included ? not included pin name:______________ active level: high ? low ?atpg test input pin .................................................................... included ? not included pin name:______________ active level: high ? low ?clear/preset input pin................................................................. included ? not included pin name:______________ active level: high ? low ?other atpg mode control pins .................................................. included ? not included a. pin name: ______________ content of control, active level, etc. : _____________________________________________________ b. pin name: ______________ content of control, active level, etc. : _____________________________________________________ c. pin name: ______________ content of control, active level, etc. : _____________________________________________________ d. pin name: ______________ content of control, active level, etc. : _____________________________________________________
chapter 2: precautions on circuit design standard cell S1K50000 series epson 29 design guide ?input pins that cannot be assigned for scan data input (note 4) ______________________________________________________________ ______________________________________________________________ ?output pins that cannot be assigned for scan data output (note 4) ______________________________________________________________ ______________________________________________________________ ?remarks ______________________________________________________________ ______________________________________________________________ ______________________________________________________________ ______________________________________________________________ ______________________________________________________________ ______________________________________________________________ ______________________________________________________________ ______________________________________________________________ number of gates (bc) prior to scan cell insertion : __________ total number of d and jk ?p-?ps : __________ expected date of trial data presentation: ( ______month, _______day, _______year) (trial data: check sheet, preliminary netlist, tentative pin arrangement table, circuit block diagram) desired fault detection rate : ____ % along with this sheet, materials that will help to con?m circuit blocks, hierarchical levels (module and instance names), and data paths between clock lines and blocks are requested. note 3: if not inserted in the original circuit, please specify your desired contents. note 4: unless a speci? request to the contrary is made, pins will be assigned by seiko epson.
chapter 2: precautions on circuit design 30 epson standard cell S1K50000 series design guide 2.11 limitations and restrictions on vhdl and verilog-hdl netlists the vhdl and verilog-hdl netlists to be interfaced to seiko epson must be in the form of pure gate-level netlists (not including an operational description). the following speci?s the limitations and restrictions to which the development of seiko epson asics by vhdl or verilog-hdl is subject. 2.11.1 common (1) external pin names (i/o pins) ?to be written entirely in uppercase letters. ?number of characterslimited to between 2 and 32 characters. ?usable characters only alphanumeric characters and underscore '_' can be used. the string must always begin with a letter, however. ?examples of unusable characters and strings: 2input: the string begins with a number. \2input: the string is pre?ed by a backslash '\'. inputa: the string includes lowercase letters. _inputa: the string begins with an underscore '_'. ina[3:0]: a bus is used for an external pin name. ina[3]: a bus is used for an external pin name. (2) internal pin names (including a bus net names) ?although a combination of uppercase and lowercase letters is permitted, the use speci- ?d below is prohibited. example: mixed use of _reset_ and _reset_, etc. ?number of characters: limited to between 2 and 32 characters ?usable characters: only alphanumeric characters, underscore '_', _[]_ (verilog bus bracket), and _()_ (vhdl bus bracket) can be used. the string must always begin with a letter, however. (3) bus description at the top of modules is prohibited. example: data[3:0], data[3], data[2], and the like are prohibited. data0, data1, data2, and the like are all permitted. (4) input/output cells must use the same library series. no cells can be used in a combination of different series. (5) operational descriptions using behavior or c language are not permitted. such descriptions in netlists have no effect. (6) all time scales in each library series are expressed to an accuracy of 1 ps.
chapter 2: precautions on circuit design standard cell S1K50000 series epson 31 design guide 2.11.2 limitations and restrictions on verilog-hdl netlists (7) descriptions using assign and tran in gate-level verilog netlists are prohibited. (8) for connecting descriptions in verilog netlists, connections using the pin names of cells are recommended. examples: pin-name connection: in2 inst_1 (.a(inst_2),.x(inst_3)); recommended net-name connection: in2 inst_1 (net1,net2); (9) verilog commands such as force cannot be used in the operational description of ?p- ?ps. (example: logic.signal = 0;) (10) a time-scale description must be added at the beginning of gate-level netlists generated by a synopsys design compiler. this time scale must have the same value as that speci?d in the seiko epson verilog library. for the time scales in each series, see (6). example: `timescale 1 ps / 1 ps (11) seiko epson prohibited the mixed use of a bus single port and the name escaped by attaching _\_ to that port within the same module, as follows: input a[0]; wire \a[0] ; (12) the strings listed below are verilogs reserved words. use of these strings as user- de?ed names is prohibited. always, and, assign, begin, buf, bu?0, bu?1, case, design,default, defparam, disable, else, end, endcase, endfunction, endmodule, endtask, event, for, force, forever, fork, function, highz0, highz1, if, initial, inout, input, integer, join, large, medium, module, nand, negedge, nor, not, notif0, notif1, or, output, parameter, posedge, pull0, pull1, reg, release, repeat, scalared, small, specify, strong0, strong1, supply0, supply1, task, time, tri, tri0, tri1, trinand, trior, trireg, vectored, wait, wand, weak0, weak1, while, wire, wor, xor, xnor
chapter 2: precautions on circuit design 32 epson standard cell S1K50000 series design guide 2.11.3 limitations and restrictions on vhdl netlists (13) in addition to the restrictions speci?d in (1), use of the following strings is also prohibited. inputa_ : the string ends with an underscore '_'. input_ _a : the string has two consecutive underscores. read : used by the system write : used by the system (14) the strings listed below are vhdls reserved words. use of these strings as user-de?ed names is prohibited. abs, access, after, alias, all, and, architecture, array, assert, attribute, begin, block, body, buffer, bus, case, component, con?uration, constant, disconnect, downto, else, elsif, end, entity, exit, ?e, for, function, generate, generic, guarded, if, in, inout, is, label, library, linkage, loop, map, mod, nand, new, next, nor, not, null, of, on, open, or, others, out, package, port, procedure, process, range, record, register, rem, report, return, select, severity, signal, subtype, then, to, transport, type, units, until, use, variable, wait, when, while, with, xor (15) before the seiko epson tools and utilities can be used, the vhdl format must be converted into verilog format. for this reason, the verilog reserved words speci?d in (12) also cannot be used in vhdl.
chapter 3: types of input/output buffers and usage precautions standard cell S1K50000 series epson 33 design guide chapter 3 types of input/output buffers and usage precautions 3.1 types of input/output buffers the S1K50000 series is available for many and varied types of cells, which can be chosen depending on the input interface level, the presence of schmitt trigger inputs or pull-up/pull- down resistors, the output drive capability, and the noise protection measures used. in accordance with the descriptions below, choose the input/output buffers best suited for your circuit. there are two methods for using the input/output buffers, one for single power supplies (3.3 v or 2.0 v) and one for dual power supplies (5.0 v and 3.3 v, or 3.3 v and 2.0 v). 3.1.1 selecting input/output buffers (1) selecting input buffers a) whether the required interface level is the cmos or ttl level b) whether a schmitt trigger input is needed (need for hysteresis characteristics) c) whether internal pull-up/pull-down resistors are required (2) selecting output buffers a) the magnitude of the required output drive current (ilo and ioh) b) whether a noise protection measure is required c) whether a bus hold circuit is required (3) selecting bidirectional buffers refer to paragraphs (1) and (2) in the selection of bidirectional buffers. ?input/output interface level 1) for dual 5.0-v power supplies input level ttl level, cmos level, ttl schmitt, cmos schmitt, pci* output level cmos level, pci* 2) for single power supplies and dual 3.3-v power supplies input level lvttl level, lvttl schmitt, pci* output level lvttl level, pci*
chapter 3: types of input/output buffers and usage precautions 34 epson standard cell S1K50000 series design guide 3) for single power supplies and dual 2.0-v power supplies input level cmos level, ttl schmitt output level cmos level note: for single power supplies (3.3 v or 2.0 v), ttl-level inputs cannot be used. * for details on the pci interface, contact seiko epson or its distributor. output drive capability see electrical characteristics (tables 1-5 through 1-7). pull-up/pull-down resistors see electrical characteristics (tables 1-5 through 1-7). beginning with the following section 3.2, ?nput/output buffer con?uration with a single power supply, we will describe in detail the procedure for con?uring the input and output buffers or bidirectional buffers with a single power supply. for details on the procedure for con?uring the input and output buffers with dual power supplies, see chapter 9, ?recautions on the use of dual power supplies.
chapter 3: types of input/output buffers and usage precautions standard cell S1K50000 series epson 35 design guide 3.2 input/output-buffer con?uration with a single power supply when input/output buffers with a single power supply are used, the power-supply voltage is either 3.3 v or 2.0 v (input/output buffers cannot be used at 5.0 v). 3.2.1 input/output-buffer con?uration with a single power supply 3.2.1.1 input-buffer con?uration with a single power supply note: when ? value is 1 or 2, the pull-up/pull-down resistance values correspond to 1:50 k ? , 2:100 k ? respectively. note: when ? value is 1 or 2, the pull-up/pull-down resistance values correspond to 1:120 k ? , 2:240 k ? respectively. table 3-1-1 input buffers (v dd = 3.3 v) cell name input level function with or without pull-up/pull-down resistors xibc xibcp ? xibcd ? lvttl lvttl lvttl buffer buffer buffer without pull-up resistor (50 k ? , 100 k ? ) pull-down resistor (50 k ? , 100 k ? ) xibh xibhp ? xibhd ? lvttl schmitt lvttl schmitt lvttl schmitt buffer buffer buffer without pull-up resistor (50 k ? , 100 k ? ) pull-down resistor (50 k ? , 100 k ? ) xibpb xibpbp ? xibpbd ? pci-3v pci-3v pci-3v buffer buffer buffer without pull-up resistor (50 k ? , 100 k ? ) pull-down resistor (50 k ? , 100 k ? ) table 3-1-2 input buffers (v dd = 2.0 v) cell name input level function with or without pull-up/pull-down resistors xibc xibcp ? xibcd ? cmos cmos cmos buffer buffer buffer without pull-up resistor (120 k ? , 240 k ? ) pull-down resistor (120 k ? , 240 k ? ) xibh xibhp ? xibhd ? cmos schmitt cmos schmitt cmos schmitt buffer buffer buffer without pull-up resistor (120 k ? , 240 k ? ) pull-down resistor (120 k ? , 240 k ? )
chapter 3: types of input/output buffers and usage precautions 36 epson standard cell S1K50000 series design guide 3.2.1.2 output-buffer con?uration with a single power supply tables 3-2-1 and 3-2-2 list the S1K50000-series output buffers. figure 3-1 example of an output-buffer symbol xob1t a ta ts used for testing output signal output output xtb1t a e ta output signal te ts enable (a) normal output buffer (b) tri-state buffer used for the output-buffer test
chapter 3: types of input/output buffers and usage precautions standard cell S1K50000 series epson 37 design guide notes: * v ol = 0.4 (v dd = 3.3 v) ** v oh = v dd - 0.4 v (v dd = 3.3 v) *** in addition to the output buffers specified in table 3-2-1, a configuration without test pins may be considered. if such a configuration is desired, contact seiko epson or its distributor. table 3-2-1 output buffers (v dd = 3.3 v) function i ol * / i oh ** cell name*** normal output 0.1 ma / -0.1 ma 1 ma / -1 ma 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xobst xobmt xob1t xob2t xob3t output for pci pci-3v xobpbt normal output for high speed 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xob1ct xob2ct xob3at normal output for low noise 12 ma / -12 ma xob3bt 3-state output 0.1 ma / -0.1 ma 1 ma / -1 ma 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xtbst xtbmt xtb1t xtb2t xtb3t 3-state output for pci pci-3v xtbpbt 3-state output for high speed 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xtb1ct xtb2ct xtb3at 3-state output for low noise 12 ma / -12 ma xtb3bt 3-state output (bus hold circuit) 1 ma / -1 ma 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xtbmht xtb1ht xtb2ht xtb3ht 3-state output for high speed (bus hold circuit) 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xtb1cht xtb2cht xtb3aht 3-state output for low noise (bus hold circuit) 12 ma / -12 ma xtb3bht
chapter 3: types of input/output buffers and usage precautions 38 epson standard cell S1K50000 series design guide notes: * v ol = 0.2 (v dd = 2.0 v) ** v oh = v dd - 0.2 v (v dd = 2.0 v) *** in addition to the output buffers specified in table 3-2-2, a configuration without test pins may be considered. if such a configuration is desired, contact seiko epson or its distributor. table 3-2-2 output buffers (v dd = 2.0 v) function i ol * / i oh ** cell name*** normal output 0.05 ma / -0.05 ma 0.3 ma / -0.3 ma 0.6 ma / -0.6 ma 2 ma / -2 ma 4 ma / -4 ma xobst xobmt xob1t xob2t xob3t normal output for high speed 0.6 ma / -0.6 ma 2 ma / -2 ma 4 ma / -4 ma xob1ct xob2ct xob3at normal output for low noise 4 ma / -4 ma xob3bt 3-state output 0.05 ma / -0.05 ma 0.3 ma / -0.3 ma 0.6 ma / -0.6 ma 2 ma / -2 ma 4 ma / -4 ma xtbst xtbmt xtb1t xtb2t xtb3t 3-state output for high speed 0.6 ma / -0.6 ma 2 ma / -2 ma 4 ma / -4 ma xtb1ct xtb2ct xtb3at 3-state output for low noise 4 ma / -4ma xtb3bt 3-state output (bus hold circuit) 0.3 ma / -0.3 ma 0.6 ma / -0.6 ma 2 ma / -2 ma 4 ma / -4 ma xtbmht xtb1ht xtb2ht xtb3ht 3-state output for high speed (bus hold circuit) 0.6 ma / -0.6 ma 2 ma / -2 ma 4 ma / -4 ma xtb1cht xtb2cht xtb3aht 3-state output for low noise (bus hold circuit) 4 ma / -4 ma xtb3bht
chapter 3: types of input/output buffers and usage precautions standard cell S1K50000 series epson 39 design guide 3.2.1.3 bidirectional-buffer con?uration with a single power supply tables 3-3-1 and 3-3-2 list the S1K50000-series bidirectional buffers. figure 3-2 example of a bidirectional-buffer symbol xbc1t a e ta used for testing output signal bidirectional te ts enable input signal
chapter 3: types of input/output buffers and usage precautions 40 epson standard cell S1K50000 series design guide notes: * v ol = 0.4 (v dd = 3.3 v) ** v oh = v dd - 0.4 v (v dd = 3.3 v) *** in addition to the bidirectional buffers specified in table 3-3-1, a configuration with pull-up/pull-down resistors or without test pins may be considered. if such a configuration is desired, contact seiko epson or its distributor. table 3-3-1 bidirectional buffers (v dd = 3.3 v) input level function i ol * / i oh ** cell name*** lvttl bi-directional output 0.1 ma / -0.1 ma 1 ma / -1 ma 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xbcst xbcmt xbc1t xbc2t xbc3t bi-directional output for high speed 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xbc1ct xbc2ct xbc3at bi-directional output for low noise 12 ma / -12 ma xbc3bt pci-3v bi-directional output for pci pci-3v xbpbt lvttl schmitt bi-directional output 0.1 ma / -0.1 ma 1 ma / -1 ma 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xbhst xbhmt xbh1t xbh2t xbh3t bi-directional output for high speed 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xbh1ct xbh2ct xbh3at bi-directional output for low noise 12 ma / -12 ma xbh3bt lvttl bi-directional output (bus hold circuit) 1 ma / -1 ma 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xbcmht xbc1ht xbc2ht xbc3ht bi-directional output for high speed (bus hold circuit) 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xbc1cht xbc2cht xbc3aht bi-directional output for low noise (bus hold circuit) 12 ma / -12 ma xbc3bht lvttl schmitt bi-directional output (bus hold circuit) 1 ma / -1 ma 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xbhmht xbh1ht xbh2ht xbh3ht bi-directional output for high speed (bus hold circuit) 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xbh1cht xbh2cht xbh3aht bi-directional output for low noise (bus hold circuit) 12 ma / -12 ma xbh3bht
chapter 3: types of input/output buffers and usage precautions standard cell S1K50000 series epson 41 design guide notes: * v ol = 0.2 (v dd = 2.0 v) ** v oh = v dd - 0.2 v (v dd = 2.0 v) *** in addition to the bidirectional buffers specified in table 3-3-2, a configuration with pull-up/pull-down resistors or without test pins may be considered. if such a configuration is desired, contact seiko epson or its distributor. table 3-3-2 bidirectional buffers (v dd = 2.0 v) input level function i ol * / i oh ** cell name*** cmos bi-directional output 0.05 ma / -0.05 ma 0.3 ma / -0.3 ma 0.6 ma / -0.6 ma 2 ma / -2 ma 4 ma / -4 ma xbcst xbcmt xbc1t xbc2t xbc3t bi-directional output for high speed 0.6 ma / -0.6 ma 2 ma / -2 ma 4 ma / -4 ma xbc1ct xbc2ct xbc3at bi-directional output for low noise 4 ma / -4 ma xbc3bt cmos schmitt bi-directional output 0.05 ma / -0.05 ma 0.3 ma / -0.3 ma 0.6 ma / -0.6 ma 2 ma / -2 ma 4 ma / -4 ma xbhst xbhmt xbh1t xbh2t xbh3t bi-directional output for high speed 0.6 ma / -0.6 ma 2 ma / -2 ma 4 ma / -4 ma xbh1ct xbh2ct xbh3at bi-directional output for low noise 4 ma / -4 ma xbh3bt cmos bi-directional output (bus hold circuit) 0.3 ma / -0.3 ma 0.6 ma / -0.6 ma 2 ma / -2 ma 4 ma / -4 ma xbcmht xbc1ht xbc2ht xbc3ht bi-directional output for high speed (bus hold circuit) 0.6 ma / -0.6 ma 2 ma / -2 ma 4 ma / -4 ma xbc1cht xbc2cht xbc3aht bi-directional output for low noise (bus hold circuit) 4 ma / -4 ma xbc3bht cmos schmitt bi-directional output (bus hold circuit) 0.3 ma / -0.3 ma 0.6 ma / -0.6 ma 2 ma / -2 ma 4 ma / -4 ma xbhmht xbh1ht xbh2ht xbh3ht bi-directional output for high speed (bus hold circuit) 0.6 ma / -0.6 ma 2 ma / -2 ma 4 ma / -4 ma xbh1cht xbh2cht xbh3aht bi-directional output for low noise (bus hold circuit) 4 ma / -4 ma xbh3bht
chapter 3: types of input/output buffers and usage precautions 42 epson standard cell S1K50000 series design guide 3.2.2 fail-safe cells (1) outline seiko epsons S1K50000 series of fail-safe cells allows signals operating at levels higher than the power-supply voltage in a single-power-supply design to be interfaced without the installation of a dedicated interfacing power supply. therefore, it is not necessary for customers to install the operating power supply or an interfacing power supply in the lsi, as is conventionally required. in addition, signals operating at levels equal to the power- supply voltage can also be interfaced without modifying the circuit. this provides customers with greater freedom in circuit design. (2) features with no limitations on the number of cells used or their placement, the fail-safe cells can be placed as desired by customers, providing freedom in circuit design. in a single-power-supply design, signals operating at levels higher than the power-supply voltage can be interfaced from the outside without the installation of a dedicated interfac- ing power supply equal to or greater than the power-supply voltage. the supported input levels are the lvttl and lvttl schmitt levels (when v dd = 3.3 v), as well as the cmos and cmos schmitt levels (when v dd = 2.0 v). because the fail-safe cells are entirely of a cmos structure, they help to reduce the chips power consumption. (3) usage precautions the fail-safe cells cannot determine seiko epsons standard input level for reasons of circuit con?uration. therefore, if it is necessary for the input level to be determined by a tester, a test circuit must be con?ured separately. in such a case, refer to the example of a test circuit on page 54 (figure 3-6) in the creation of a test circuit. the fail-safe cells are characterized in that when the output pins are in high-z state, i.e., in input mode, no dc current will ?w into the lsi even when signals exceeding the power-supply voltage are fed into the pins. however, if signals equal to or greater than the power-supply voltage are fed into the pins when the cell is in output mode and output- ting a high-level signal, dc current will ?w into the lsi as with a conventional fail-safe cell. this occurs in a situation in which, while the fail-safe cell is outputting a high-level (3.3 v) signal, another device is also outputting a high-level (5.0 v) signal at the same time. note that the other device referred to here includes a pull-up resistor. although signals with a voltage level equal to or greater than the lsis operating voltage can be accepted, in no case can the signal voltages applied to the fail-safe cell exceed the absolute maximum rated voltage.
chapter 3: types of input/output buffers and usage precautions standard cell S1K50000 series epson 43 design guide (4) list of fail-safe cells fail-safe input buffers this is an input cell with the protective diode on the v dd side eliminated. this input buffer is used in cases in which, in a single power-supply system, high-voltage signals above v dd are entered (for example, 5-v signals when v dd = 3.3 v, or 3.3-v signals when v dd = 2.0 v). the input level of this buffer when v dd = 2.0 v is the cmos level. note: the indicated resistance values apply to the case where v dd = 3.3 v. fail-safe output buffers 1) n-channel open-drain type this output buffer is used in cases in which, in a 3-v single-power-supply system, 5.0- v signals are output. with the p-channel removed, this type of buffer can only output a low-level signal but, by tying the pull-up resistors external to the standard cell to 5 v, it can send 5-v signals to external 5-v devices. 2) tri-state type in ordinary tri-state output buffers, if a 5-v system voltage propagates while their outputs are disabled (hi-z state), dc current ?ws into the internal part of the asic chip. the fail-safe cell, however, is constructed so as to prevent such a current from ?wing in. furthermore, it can output a 3-v-system full-swing signal. unlike the n- channel open-drain type, however, this type of fail-safe cell cannot have its output pulled high to 5 v through the addition of a pull-up resistor external to the standard cell. table 3-4-1 fail-safe input buffers (v dd = 3.3 v) input level without resistor pull-down* pull-up* 50 k ? 100 k ? 50 k ? 100 k ? lvttl xidc xidcd1 xidcd2 xibbp1 xibbp2 lvttl schmitt xidh xidhd1 xidhd2
chapter 3: types of input/output buffers and usage precautions 44 epson standard cell S1K50000 series design guide notes: * v ol = 0.4 v (v dd = 3.3 v) ** in addition to those specified in table 3-4-2, cells without test pins are also available. if such cells are desired, contact seiko epson or its distributor. table 3-4-2 fail-safe output buffers (v dd = 3.3 v) function i ol * cell name n-channel open-drain** tri-state normal output 2 ma xod1t xtbf1 6 ma xod2t xtbf2 12 ma xod3t high speed output 2 ma xod1ct xtbf1c 6 ma xod2ct xtbf2c 12 ma xtbf3a
chapter 3: types of input/output buffers and usage precautions standard cell S1K50000 series epson 45 design guide fail-safe bidirectional buffers 1) n-channel open-drain type notes: * v ol = 0.4 v (v dd = 3.3 v) ** in addition to the n-channel open-drain bidirectional buffers specified in table 3-4-3, a bidirectional-buffer configuration without test pins may be considered. if such a test-pinless configuration is desired, contact seiko epson or its distributor. figure 3-3 example of an n-channel open-drain bidirectional-buffer symbol table 3-4-3 n-channel open-drain bidirectional buffers (v dd = 3.3 v) input level function i ol * cell name** lvttl bi-directional output 2 ma 6 ma 12 ma bdc1t bdc2t bdc3t bi-directional output for high speed 2 ma 6 ma bdc1ct bdc2ct lvttlschmitt bi-directional output 2 ma 6 ma 12 ma bdh1t bdh2t bdh3t bi-directional output for high speed 2 ma 6 ma bdh1ct bdh2ct bdc1t a e ta used for testing output signal bidirectional te ts enable input signal
chapter 3: types of input/output buffers and usage precautions 46 epson standard cell S1K50000 series design guide 2) tri-state type as with tri-state output buffers, this type of cell cannot have its output pulled high to 5 v through the addition of a pull-up resistor external to the standard cell. *1: the indicated resistance values apply to cases where v dd = 3.3 v. figure 3-4 typical configuration of a fail-safe cell table 3-4-4 fail-safe cell bidirectional buffers (v dd = 3.3 v) input level drain type test function output latch function speed output current (ma) *1 without a resistor pull-down *1 pull-up *1 50 k ? 100 k ? 50 k ? 100 k ? lvttl fail- safe n/a n/a normal -2 / 2 bb1 bb1d1 bb1d2 bb1p1 bb1p2 -6 / 6 bb2 bb2d1 bb2d2 bb2p1 bb2p2 high- speed -2 / 2 bb1c bb1cd1 bb1cd2 bb1cp1 bb1cp2 -6 / 6 bb2c bb2cd1 bb2cd2 bb2cp1 bb2cp2 -12 / 12 bb3a bb3ad1 bb3ad2 bb3ap1 bb3ap2 lvttl schmitt fail- safe n/a n/a normal -2 / 2 bg1 bg1d1 bg1d2 -6 / 6 bg2 bg2d1 bg2d2 high- speed -2 / 2 bg1c bg1cd1 bg1cd2 -6 / 6 bg2c bg2cd1 bg2cd2 -12 / 12 bg3a bg3ad1 bg3ad2 bg3ap1 bg3ap2 v dd = 3.3 v i/o cell area 5-v input 5 v 3.3-v output 3.3-v output 5-v input 5-v output internal: 3.3 v vss fail-safe input: xidc n-channel open-drain output: xod1t fail-safe output: xtbf1 fail-safe bidirectional: xbb1
chapter 3: types of input/output buffers and usage precautions standard cell S1K50000 series epson 47 design guide 3.3 con?uration of oscillator circuits 3.3.1 when con?uring an oscillator circuit in the con?uration of an oscillator circuit, one of the con?urations shown in figure 3-5 applies, depending on the oscillator cell used. the input and output cells used in this case are a combination of xlin and xlout. figure 3-5 method for configuration of an oscillator circuit xlin oscillator cell internal to the ic xlot for continuous oscillation xlin oscillator cell internal to the ic xlot for intermittent oscillation gx d gx d e cg cd rf rd x tal cg cd rf rd x tal xa pa d pa d xa pa d pa d
chapter 3: types of input/output buffers and usage precautions 48 epson standard cell S1K50000 series design guide 3.3.2 precautions on the use of oscillator circuits (1) pin arrangement position the oscillator circuits input/output pins adjacent to each other, and position the power-supply pins (v dd and v ss ) on either side of those input/output pins. do not position other output pins adjacent to the oscillator circuits input/output pins. in particular, outputs in phase or out of phase with the oscillators waveform cannot be posi- tioned close to the input/output pins. make sure these outputs are positioned on the opposite side of the package. try to position the oscillator circuits input/output pins as close to the center as possible on the side of the package. (2) guide to selection of the oscillator cell the possible oscillation frequencies are on the order of several 10 khz to several 10 mhz. for details, contact seiko epson or its distributor. (3) setting external resistor and capacitor values the oscillation characteristics depend on the various components (ic, x?al, rf, rd, cg, cd, and the circuit board) that comprise the circuit. therefore, be sure to choose the most suitable values for rf, rd, cg, and cd after carefully evaluating the performance of each part while mounted on the actual board. (4) guaranteed level the oscillation characteristics depend on the various components (ic, x?al, rf, rd, cg, cd, and the circuit board) that comprise the circuit. therefore, seiko epson cannot guarantee the operation and characteristics of the oscillator. customers are requested to verify the oscillation characteristics by performing careful evaluation using an es sample. (5) oscillator-circuit con?uration with dual power supplies the oscillator-circuit con?uration in this case is basically the same as in the case of a single-power-supply con?uration. because the oscillator cell is connected to the lv dd - system power supply, use the input and output cells labeled ?llin and ?llot, with the letter ? pre?ed to xlin and xlot.
chapter 3: types of input/output buffers and usage precautions standard cell S1K50000 series epson 49 design guide 3.4 gated i/o cells 3.4.1 outline of gated i/o cells seiko epsons S1K50000 series of gated i/o cells make it possible to provide input to pins in the ?ating or hi-z state without the use of pull-up or pull-down circuits, an operation that was conventionally impossible. they also make it possible to cut off the high-voltage-side (hv dd ) power supply in a multi-power-supply design. two types are available: one in which the power supply is cut off when the control-signal level is high, and another in which the power supply is cut off when the control-signal level is low, allowing the level for cutting off the power supply to be chosen in accordance with the circuit design. 3.4.2 features of gated i/o cells (1) without limitations on the number of cells used or their placement, the gated i/o cells can be positioned as desired by customers, providing freedom in circuit design. (2) in a multi-power-supply design, the high-voltage-side (hv dd ) power supply can be cut off. however, because special measures are needed, if such a cut-off function is desired, contact seiko epson or its distributor. (3) inputs can be placed in the hi-z state without the use of pull-up or pull-down circuits. (4) the supported input levels are the ttl level (when hv dd and lv dd = 5.0 v and 3.3 v) or the lvttl level (when hv dd and lv dd = both 3.3 v; or v dd = 3.3 v). (5) two types are available: one in which the power supply is cut off when the control-signal level is high, and another in which the power supply is cut off when the control-signal level is low. (6) because the gated i/o cells are entirely of a cmos structure, they help to reduce the chips power consumption. 3.4.3 precautions on the use of gated i/o cells (1) the gated i/o cells cannot be subjected to seiko epsons standard input-level determination due to the circuit con?uration. therefore, if it is necessary for the input level to be determined by a tester, a test circuit must be con?ured separately. for an example of a test circuit, see figure 3-6. (2) when inputs are placed in the hi-z state using gated i/o cells, the power supply must be cut off through control of the gated i/o cell before the pin inputs ?at to a hi-z state. if inputs are placed in the hi-z state without the performance of this cut-off, a large current ?ws into the lsi as with ordinary cells, causing the device to malfunction. the same applies to the performance of connecting operations using control of the gated i/o cell while inputs are left ?ating. in such a case, the logic levels latched into the devices internal logic cannot be guaranteed. before you cut off the power to the high-voltage side (hv dd ), ?st contact epsons marketing division, as a special procedure is also required in this case.
chapter 3: types of input/output buffers and usage precautions 50 epson standard cell S1K50000 series design guide (3) the same processing as speci?d in (2) is also necessary when the high-voltage-side (hv dd ) power supply is cut off through the use of a gated i/o cell. unless this processing is performed, the logic levels latched into the devices internal logic cannot be guaranteed. in addition, because special measures are required, if such a cut-off operation is desired, please contact seiko epson or its distributor. *1: the indicated resistance values apply to cases where v dd = 3.3 v. *1: the indicated resistance values apply to cases where hv dd = 5.0 v. *1: the indicated resistance values apply to cases where v dd = 3.3 v. table 3-5-1 gated input cells (v dd = 3.3 v, 2.0 v) drain type input level without a resistor pull-down *1 pull-up *1 50 k ? 100 k ? 50 k ? 100 k ? normal cmos and xiba xibad1 xibad2 xibap1 xibap2 or xibo xibod1 xibod2 xibop1 xibop2 table 3-5-2 gated input cells (hv dd = 5.0 v, 3.3 v, 2.0 v) drain type input level without a resistor pull-down *1 pull-up *1 60 k ? 120 k ? 60 k ? 120 k ? normal cmos and xhiba xhibad1 xhibad2 xhibap1 xhibap2 or xhibo xhibod1 xhibod2 xhibop1 xhibop2 table 3-5-3 gated bidirectional cells (and type, v dd = 3.3 v, 2.0 v) input level drain type test function output latch function speed output current (ma) *1 without a resistor pull-down *1 pull-up *1 50 k ? 100 k ? 50 k ? 100 k ? cmos normal available n/a normal -2 / 2 xba1t xba1d1t xba1d2t xba1p1t xba1p2t -6 / 6 xba2t xba2d1t xba2d2t xba2p1t xba2p2t -12 / 12 xba3t xba3d1t xba3d2t xba3p1t xba3p2t high speed -2 / 2 xba1ct xba1cd1t xba1cd2t xba1cp1t xba1cp2t -6 / 6 xba2ct xba2cd1t xba2cd2t xba2cp1t xba2cp2t -12 / 12 xba3at xba3ad1t xba3ad2t xba3ap1t xba3ap2t low noise -12 / 12 xba3bt xba3bd1t xba3bd2t xba3bp1t xba3bp2t n/a n/a normal -2 / 2 xba1 xba1d1 xba1d2 xba1p1 xba1p2 -6 / 6 xba2 xba2d1 xba2d2 xba2p1 xba2p2 -12 / 12 xba3 xba3d1 xba3d2 xba3p1 xba3p2 high speed -2 / 2 xba1c xba1cd1 xba1cd2 xba1cp1 xba1cp2 -6 / 6 xba2c xba2cd1 xba2cd2 xba2cp1 xba2cp2 -12 / 12 xba3a xba3ad1 xba3ad2 xba3ap1 xba3ap2 low noise -12 / 12 xba3b xba3bd1 xba3bd2 xba3bp1 xba3bp2
chapter 3: types of input/output buffers and usage precautions standard cell S1K50000 series epson 51 design guide *1: the indicated resistance values apply to cases where v dd = 3.3 v. table 3-5-4 gated bidirectional cells (or type, v dd = 3.3 v, 2.0 v) input level drain type test function output latch function speed output current (ma) *1 without a resistor pull-down *1 pull-up *1 50 k ? 100 k ? 50 k ? 100 k ? cmos normal available n/a normal -2 / 2 xbo1t xbo1d1t xbo1d2t xbo1p1t xbo1p2t -6 / 6 xbo2t xbo2d1t xbo2d2t xbo2p1t xbo2p2t -12 / 12 xbo3t xbo3d1t xbo3d2t xbo3p1t xbo3p2t high speed -2 / 2 xbo1ct xbo1cd1t xbo1cd2t xbo1cp1t xbo1cp2t -6 / 6 xbo2ct xbo2cd1t xbo2cd2t xbo2cp1t xbo2cp2t -12 / 12 xbo3at xbo3ad1t xbo3ad2t xbo3ap1t xbo3ap2t low noise -12 / 12 xbo3bt xbo3bd1t xbo3bd2t xbo3bp1t xbo3bp2t n/a n/a normal -2 / 2 xbo1 xbo1d1 xbo1d2 xbo1p1 xbo1p2 -6 / 6 xbo2 xbo2d1 xbo2d2 xbo2p1 xbo2p2 -12 / 12 xbo3 xbo3d1 xbo3d2 xbo3p1 xbo3p2 high speed -2 / 2 xbo1c xbo1cd1 xbo1cd2 xbo1cp1 xbo1cp2 -6 / 6 xbo2c xbo2cd1 xbo2cd2 xbo2cp1 xbo2cp2 -12 / 12 xbo3a xbo3ad1 xbo3ad2 xbo3ap1 xbo3ap2 low noise -12 / 12 xbo3b xbo3bd1 xbo3bd2 xbo3bp1 xbo3bp2
chapter 3: types of input/output buffers and usage precautions 52 epson standard cell S1K50000 series design guide *1: the indicated resistance values apply to cases where hv dd = 5.0 v. *1: the indicated resistance values apply to cases where hv dd = 5.0 v. table 3-5-5 gated bidirectional cells (and type, hv dd = 5.0 v, 3.3 v, 2.0 v) input level drain type test function output latch function speed output current (ma) *1 without a resistor pull-down *1 pull-up *1 60 k ? 120 k ? 60 k ? 120 k ? cmos normal available n/a normal -3 / 3 xhba1t xhba1d1t xhba1d2t xhba1p1t xhba1p2t -8 / 8 xhba2t xhba2d1t xhba2d2t xhba2p1t xhba2p2t -12 / 12 xhba3t xhba3d1t xhba3d2t xhba3p1t xhba3p2t high speed -12 / 12 xhba3at xhba3ad1t xhba3ad2t xhba3ap1t xhba3ap2t low noise -12 / 12 xhba3bt xhba3bd1t xhba3bd2t xhba3bp1t xhba3bp2t n/a n/a normal -3 / 3 xhba1 xhba1d1 xhba1d2 xhba1p1 xhba1p2 -8 / 8 xhba2 xhba2d1 xhba2d2 xhba2p1 xhba2p2 -12 / 12 xhba3 xhba3d1 xhba3d2 xhba3p1 xhba3p2 high speed -12 / 12 xhba3a xhba3ad1 xhba3ad2 xhba3ap1 xhba3ap2 low noise -12 / 12 xhba3b xhba3bd1 xhba3bd2 xhba3bp1 xhba3bp2 table 3-5-6 gated bidirectional cells (and type, hv dd = 5.0 v only) input level drain type test function output latch function speed output current (ma) *1 without a resistor pull-down *1 pull-up *1 60 k ? 120 k ? 60 k ? 120 k ? cmos normal available n/a normal -12 / 24 xhba4t xhba4d1t xhba4d2t xhba4p1t xhba4p2t high speed -12 / 24 xhba4at xhba4ad1t xhba4ad2t xhba4ap1t xhba4ap2t low noise -12 / 24 xhba4bt xhba4bd1t xhba4bd2t xhba4bp1t xhba4bp2t n/a n/a normal -12 / 24 xhba4 xhba4d1 xhba4d2 xhba4p1 xhba4p2 high speed -12 / 24 xhba4a xhba4ad1 xhba4ad2 xhba4ap1 xhba4ap2 low noise -12 / 24 xhba4b xhba4bd1 xhba4bd2 xhba4bp1 xhba4bp2
chapter 3: types of input/output buffers and usage precautions standard cell S1K50000 series epson 53 design guide *1: the indicated resistance values apply to cases where hv dd = 5.0 v. *1: the indicated resistance values apply to cases where hv dd = 5.0 v. table 3-5-7 gated bidirectional cells (or type, hv dd = 5.0 v, 3.3 v, 2.0 v) input level drain type test function output latch function speed output current (ma) *1 without a resistor pull-down *1 pull-up *1 60 k ? 120 k ? 60 k ? 120 k ? cmos normal available n/a normal -3 / 3 xhbo1t xhbo1d1t xhbo1d2t xhbo1p1t xhbo1p2t -8 / 8 xhbo2t xhbo2d1t xhbo2d2t xhbo2p1t xhbo2p2t -12 / 12 xhbot xhbo3d1t xhbo3d2t xhbo3p1t xhbo3p2t high speed -12 / 12 xhbo3at xhbo3ad1t xhbo3ad2t xhbo3ap1t xhbo3ap2t low noise -12 / 12 xhbo3bt xhbo3bd1t xhbo3bd2t xhbo3bp1t xhbo3bp2t n/a n/a normal -3 / 3 xhbo1 xhbo1d1 xhbo1d2 xhbo1p1 xhbo1p2 -8 / 8 xhbo2 xhbo2d1 xhbo2d2 xhbo2p1 xhbo2p2 -12 / 12 xhbo3 xhbo3d1 xhbo3d2 xhbo3p1 xhbo3p2 high speed -12 / 12 xhbo3a xhbo3ad1 xhbo3ad2 xhbo3ap1 xhbo3ap2 low noise -12 / 12 xhbo3b xhbo3bd1 xhbo3bd2 xhbo3bp1 xhbo3bp2 table 3-5-8 gated bidirectional cells (or type, hv dd = 5.0 v only) input level drain type test function output latch function speed output current (ma) *1 without a resistor pull-down *1 pull-up *1 60 k ? 120 k ? 60 k ? 120 k ? cmos normal available n/a normal -12 / 24 xhbo4t xhbo4d1t xhbo4d2t xhbo4p1t xhbo4p2t high speed -12 / 24 xhbo4at xhbo4ad1t xhbo4ad2t xhbo4ap1t xhbo4ap2t low noise -12 / 24 xhbo4bt xhbo4bd1t xhbo4bd2t xhbo4bp1t xhbo4bp2t n/a n/a normal -12 / 24 xhbo4 xhbo4d1 xhbo4d2 xhbo4p1 xhbo4p2 high speed -12 / 24 xhbo4a xhbo4ad1 xhbo4ad2 xhbo4ap1 xhbo4ap2 low noise -12 / 24 xhbo4b xhbo4bd1 xhbo4bd2 xhbo4bp1 xhbo4bp2
chapter 3: types of input/output buffers and usage precautions 54 epson standard cell S1K50000 series design guide figure 3-6 typical test circuit for fail-safe and gated cells in the example circuit shown above, single-power-supply and dual-power-supply i/o cells coexist for reasons of convenience. please be aware that in actual circuits these two types of cells cannot coexist. user0 user1 user2 ip0 ip1 ip2 tsten test1 tm0 td ms kad3 tm1 tm2 tst ilg te ts tac olg ktcir xibc xibc xibc xibc user logic xitst1 xhbt1t xhba1t kor2 a e xbb1 kao24a kao24a a e ta te ts a e ta te ts bidir3 bidir2 bidir1 bidir0 xhob1t a ta ts out1 kad2 kad2 kad2 xhiba xhiba kad2 kad2 a e xbb1 kao24a kao24a xhob1t a ta ts out0 kor2 kor2
chapter 4: circuit design taking testability into account standard cell S1K50000 series epson 55 design guide chapter 4 circuit design taking testability into account prior to the shipment of standard cells from the factory, a product test is conducted through the use of an lsi tester. therefore, testability must fully be taken into account in the circuit design. consider the following points in the design of a circuit. 4.1 consideration for circuit initialization many ?p-?ps are used in a circuit. however, when tests are conducted using an lsi tester or a circuit is simulated, all of the ?p-?ps in the initial state are in an x (indeterminate) state. therefore, depending on the circuit con?uration, it will be impossible to initialize the circuit, or a huge test pattern may be required for initialization. therefore, in the design of a circuit, use ?p-?ps with a reset input or take other similar measures to ensure that the circuit can be initialized easily. 4.2 consideration for reduction of the test-pattern size as the circuit size increases, so does the size of the test pattern. however, test patterns are subject to the following limitations imposed by an lsi tester. number of events per test pattern : up to 256k number of test patterns : up to 30 total number of events in test patterns : within 1m these limitations apply to all types of test patterns, such as those for dc testing, for z inspection, for a test circuit, and rom or megacell test patterns prepared by seiko epson. for details on the number of rom and megacell test patters and the number of events in those test patterns, contact seiko epson or its distributor. regarding test patterns for ram testing, please note that although the reference patterns prepared by customers are included in those that are subject to said limitations, the full test patterns for ram to be prepared by seiko epson are not included. in the design of a circuit, incorporate measures to increase its testability, thereby reducing the size of the test patterns required for it by, for example, installing a test pin that allows a clock to be fed into the middle of multistage counters or adding a test pin that allows the lsis internal signals to be monitored.
chapter 4: circuit design taking testability into account 56 epson standard cell S1K50000 series design guide 4.3 circuit con?uration to facilitate dc and ac tests 4.3.1 con?uration of a test circuit the S1K50000 series requires a test-circuit con?uration allowing dc and ac tests to be conducted ef?iently. if such a test circuit is not con?ured in your circuit design, contact seiko epson or its distributor for con?mation. figure 4-1 shows an example of a test circuit. use this circuit for reference purposes in the design of a test circuit. note that several input and output pins are required for use with a test circuit. (1) adding and selecting pins used for testing add and select the following four types of test pins. test-mode switch pin : 1 pc. ? test-mode select input pin : 3 pcs. ac test monitor output pin : 1 pc. dc test monitor output pin : 1 pc. table 4-1 restrictions on test pins type of test pin number of pins pin name (example) restrictions, etc. test-mode switch pin 1 pc. tsten dedicated input pin. use xitst1 for the input buffer. high: test mode; low: normal mode test-mode select input pin 3 pcs. inp0 inp1 inp2 shareable input pin. this pin cannot be shared with bidirectional pins. avoid sharing this pin with input pins that have a critical path. ac test monitor output pin 1 pc. out3 shareable output pin. this pin cannot be shared with bidirectional 3-state pins or n-channel open-drain cells. output buffers type s and type m cannot be used. dc test monitor output pin 1 pc. out4 shareable output pin. this pin cannot be shared with bidirectional 3-state pins or n-channel open-drain cells. output and input/output pins use an input/output buffer with a test mode.
chapter 4: circuit design taking testability into account standard cell S1K50000 series epson 57 design guide (2) dc test measurement is conducted to determine whether all of the input and output pins satisfy the speci?ations associated with dc characteristics. if a test circuit is not available, customers will be requested to create a test pattern that makes it possible to measure dc characteristics. many man-hours may be required to create this test pattern. use of a test circuit makes it easy to create a test pattern and measure dc characteristics. (3) ac test measurement is made of the pin-to-pin (input pin to output pin) speed. in cases in which the actual operating frequency cannot be inspected by an lsi tester, the operating speed can be guaranteed by measuring the delay in a speci? path. the ac test monitor output pin is used to evaluate lot-to-lot dispersion at seiko epson by measuring a dedicated ac path (cell name: kacp1). (when using a test circuit, be sure to insert kacp1 in its design.) (4) adding a test-mode control circuit an example circuit in cases in which you con?ure a test circuit is shown below. refer to the example test circuit shown in figure 4-1. a. select four test input pins and two output pins. test-mode switch pin : 1 pc. test-mode select input pin (shared input pin) : 3 pcs. ac test monitor output pin (shared output pin) : 1 pc. dc test monitor output pin (shared output pin) : 1 pc. b. use the input cell xitst1 for the test-mode select input pins (inp0, 1, 2). c. the input buffers for the test-mode select input pins (inp0, 1, 2) vary depending on the input buffers of the user application. however, avoid sharing these pins with input pins that have a critical path. d. the output buffers of the test monitor output pins (out3, out4) vary depending on the output buffers of the user application. however, avoid sharing these pins with output pins that have a critical path. e. for all output and bidirectional pins, be sure to use input/output buffers with a test mode. f. create a test-mode control circuit (ktcir), and include it in the circuit design. g. make sure the input buffer (xitst1) for the test-mode switch pin has its output pins x and lg connected to the tst and ilg pins of the ktcir.
chapter 4: circuit design taking testability into account 58 epson standard cell S1K50000 series design guide h. make sure the input buffers for the test-mode select input pins have their outputs connected to the input pins of the ktcir. connect the inp0 input buffers output to the tm0 pin of the ktcir. connect the inp1 input buffers output to the tm1 pin of the ktcir. connect the inp2 input buffers output to the tm2 pin of the ktcir. i. make sure the output pins of the test-mode control circuit (ktcir) are connected to the input pins of the input/output buffers. connect the ktcirs output pin (tac) to the ta pin of the ac test monitor output pin (out3)s input/output buffer. connect the ktcirs output pin (ts) to the ts pins of all input/output buffers. connect the ktcirs output pin (td) to the ta pins of all input/output buffers, except for the test monitor output pins (out3, out4). connect the ktcirs output pin (te) to the te pins of the input/output buffers of the tri- state pin (out2) and bidirectional pin (bid1). connect the ktcirs output pin (olg) to the ta pin of the dc test monitor output pin (out4)s input/output buffer. j. use the ktcirs output pin (ms) to control each macro when ram and functional cells are included. k. adjust the signals to the input/output buffers ta, te, and ts pins, to ensure that their fan-out limits will not be exceeded. (5) setting the test mode a. dc test quiescent-current measurement mode tsten . . . high output-characteristic (v oh /v ol ) measurement mode tsten . . . high inp0 . . . low inp1 . . . high/low input inp2 . . . low input-characteristic (v ih /v il ) measurement mode tsten . . . high measured pin *1 . . . high/low input unmeasured pin . . . high *1: apply to all input and bidirectional pins, except for testen.
chapter 4: circuit design taking testability into account standard cell S1K50000 series epson 59 design guide b. dedicated ac path measurement mode tsten . . . high inp0 . . . low inp1 . . . low inp2 . . . high/low input 6) creating test patterns in order for ac and dc tests to be conducted ef?iently, customers are requested to design a test circuit as well as a test pattern. figure 4-2 shows an example test pattern for the example test circuit shown in figure 4-1. note the following in the design of a test pattern: a. create a test pattern like the one shown in the example separately from the patterns used to verify the circuits functionality. seiko epson creates only the test patterns of the input logic level inspection mode. b. all pins used in the circuit must be written in this test pattern. c. also write test pins (e.g., tsten) in the patterns used to verify the circuits functionality. in such a case, make sure the input level of the test pin (e.g., tsten) is low (= 0). d. when the input level of the test pin (e.g., tsten) is high (= 1), all of the pull-up/pull- down resistors are disabled (inactive). table 4-2 test-circuit truth table input output tst ilg tm2 tm1 tm0 ts td te tac olg ms 0xxxx 000000 11xxx1xxx1x 10xxx1xxx0x 1x1111111x0 1x1101111x0 1x1011111x0 1x0111111x0 1x0011101x1 1x0101101x0 1x1001001x0 1x0001000x0
chapter 4: circuit design taking testability into account 60 epson standard cell S1K50000 series design guide figure 4-1 example of a test circuit xibc in inp0 inp1 inp2 tsten xibc xibc xibc xitst1 tm0 tm1 tm2 td ms ts te tac i_2 ktcir out1 a ta ts xob1t bid1 a e ta xtb1t te ts tst ilg olg application circuit out2 out4 a ta ts xob1t out3 a ta ts xob1t a e ta te ts xbc1t tm0 tst tm1 tm2 td olg tac ms te ts ilg
chapter 4: circuit design taking testability into account standard cell S1K50000 series epson 61 design guide figure 4-2 example of a test pattern created for a test option $rate 200000 $strobe 185000 $resolutio n 0.001ns $node tsten i 0 inp0 i 0 inp1 i 0 inp2 i 0 in i 0 bid1 bu 0 out1 0 out2 0 out3 0 out4 0 $endnode $pattern * example of test pattern forac & dc test note: a period (.) denotes a 1 or 0. tiiiiboooo snnnniuuuu tppp dtttt e012 11234 n iiiiiboooo u # # # # # # # # # $ endpattern # # eof 0 0000.xxxxx 1 1000.llllx 2 1000.llllx 3 1001.lllhx 4 1000.llllx 5 1101.0hzhx 6 1101.1hzhx 7 1000.llllx 8 1010.hhhhx ; pull-up/down off ; ac path output (high), other outputs (low) ; ac path output (low), other outputs (low) ; ac path output (low), other outputs (low) ; off state, normal output (high) (input low) ; off state, normal output (high) (input high) ; output (low) ; output (high) ? ? ? ? ? ? ? ?
chapter 4: circuit design taking testability into account 62 epson standard cell S1K50000 series design guide 4.4 test circuit for functional cells when functional cells are used, huge numbers of test patterns and large amounts of time are required to verify the operation of the entire circuit (including the user circuit). therefore, customers are requested to design a test circuit in such a way that operation of the functional cells and user circuit can be veri?d as single units. in the design of a test circuit, note the following. 4.4.1 con?uration of a test circuit (1) add a test circuit so that each functional cell and the user circuit can be separated and measured individually for each block, with the pins of the functional cells leading out to external pins. (2) even when ?ing the inputs of the functional cells to v ss or v dd , install a test circuit to enable test input. (3) even when not using the output pins of the functional cells, install a test circuit to allow all outputs of the functional cells to be observed from external pins. (4) do not use multiple output or input pins of the functional cells collectively as one test- shareable pin. (5) do not use a sequential circuit in a test circuit that is used to test the functional cells. (6) do not feed an input signal from the test input pin into the function cells after inverting its logic level. in addition, do not forward the output signals of the functional cells to the test output pin after inverting their logic level. (7) if the functional cells input and output pins are led out directly as pins of the ic, it is not necessary to attach a test circuit. (8) do not use bidirectional buffers with a pull-up for the test-mode switch pin. bidirectional buffers with a pull-down are acceptable. 4.4.2 test patterns broadly classi?d, there are the following three types of test patterns: 1) test pattern for testing only the user circuit 2) test pattern for testing the entire circuit 3) test pattern for testing only the functional cells the test patterns that must be created by customers are items 1) and 2) above. the test pattern in item 3) does not need to be created by customers. existing test patterns at seiko epson are used. please note, however, that the test patterns for the functional cells (i.e., the existing test patterns) cannot be disclosed to customers.
chapter 4: circuit design taking testability into account standard cell S1K50000 series epson 63 design guide 4.4.3 test-circuit information customers are requested to provide the following information regarding a test circuit, as it is necessary to test the functional cells during simulation and shipment inspection: (1) clearly indicate which pins of the function cells are connected to which pins of the ic in test mode. (2) if a test circuit is con?ured to allow multiple functional cells to be tested from a single test pin, clearly indicate the relationship between the test mode and the selected functional-cell names. (3) particularly when using two or more of the same functional cell, assign the functional-cell names a sequential number in the drawing, clearly indicating for which functional cell the test pin is used. (4) clearly indicate the method for switching to test mode.
chapter 5: propagation delay time and timing design 64 epson standard cell S1K50000 series design guide chapter 5 propagation delay time and timing design the delay time in an lsi is determined by the delay time in each cell itself, and by delays caused by capacitive loads such as wiring and input capacitances connected to the outputs of those cells. the delay time ?ctuates depending on the power-supply voltage, ambient temperature, and process conditions. it also ?ctuates in accordance with factors associated with the circuit con?uration, such as input waveforms, input logic levels, and mirror effects. the S1K50000 series offers a highly accurate delay calculation environment in which these ?ctuating factors are taken into account. therefore, please note that the delay calculations differ from those performed using the values listed in the ?tandard cell S1K50000-series msi cell library described later. 5.1 precautions regarding the relationship between ta and tj the delay in a cmos ic basically ?ctuates with tj (junction temperature). ic speci?ations, on the other hand, are generally represented by ta (ambient temperature). however, the relationship between tj and ta is not constant; it varies depending on the packages thermal resistance and the power consumption of that ic. (for details, see section 7.2, ?ower- consumption limitations.) for asics, the packages thermal resistance and the power consumption vary with each circuit and application. therefore, strictly speaking, speci?ation examination based on ta is dif?ult. as a result, delay libraries are available with seiko epsons S1K50000 series to help you verify the circuit design at its early stage with respect to the approximate guidelines given below. * tj = 0 to 85 [?] library for ta = 0 to 70 [?] * tj = -40 to 125 [?] library for ta = -40 to 85 [?] of course, if the relationship between ta and tj varies signi?antly when the packages thermal resistance and the power consumption are estimated, customers will be recommended to use the tj = -40 to 125 [?] library for ta = 0 to 70 [?], or requested to have other conditions added.
chapter 5: propagation delay time and timing design standard cell S1K50000 series epson 65 design guide 5.2 simpli?d delay models the propagation delay time, tpd, is obtained using the equation shown below. t pd = t 0 + k ( load a + load b) where t 0 : nonloaded delay [ps] k : coef?ient of loaded delay [ps/lu] load a : input load capacitance of the connected cell [lu] load b : wiring load capacitance [lu] note: the values of t 0 and k vary depending on the operating voltage, ambient temperature, and process conditions. use the values listed in the cell library. the typ. values of t 0 and k (v dd = center value; ta = 25?, process = center value) are listed in the ?tandard cell S1K50000-series msi cell library. choose the typ. values of t 0 and k in accordance with the intended power-supply voltage. the min. values of t 0 and k (v dd = highest value; ta = lowest value; process = fast) and max. values (v dd = lowest value; ta = highest value; process = slow) can be obtained by multiplying said typ. values by a dispersion coef?ient of delay, m. (these min. and max. values are important in verifying that the delay in the circuit is within the desired speci?ations, even in the presence of dispersions in v dd , ta, or the process.) the dispersion coef?ient of delay, m, is calculated as follows: m = mv mt mp where mv : coef?ient of power-supply-voltage ?ctuation mt : coef?ient of ambient-temperature ?ctuation mp : coef?ient of process ?ctuation although mv and mt can be read out from the characteristic graphs shown in the ?tandard cell S1K50000-series msi cell library, we recommend use of the standard dispersion coef?ients of delay, m, listed in table 5-1 below. for the dispersion coef?ients of delay outside the standard power-supply-voltage and ambient-temperature ranges, contact seiko epson or its distributor. note 1: the delay in a predriver with a level shifter cannot be obtained simply by multiplying the typ. value by a dispersion coefficient of delay, as described above. precalculated min. and max. values are listed along with the typ. values in the ?tandard cell S1K50000-series msi cell library.? see section 9.4, ?alculating the delay time in a dual-power-supply system,?in this manual.
chapter 5: propagation delay time and timing design 66 epson standard cell S1K50000 series design guide values enclosed in ( ) are those for i/o buffers; otherwise, the values are for msi cells. *1: this temperature range assumes tj = 0? to 85?. *2: this temperature range assumes tj = -40? to 125?. table 5-1 dispersion coef?ient of delay, m (ordinary functional cells) conditions m value usage min. ty p. max. power-supply voltage: 5.0 v ?5% ta : 0 to 70?* 1 (0.70) (1.00) (1.48) use this to multiply the typ. values of t 0 and k at hv dd = 5.0 v. power-supply voltage: 5.0 v ?10% ta : -40 to 85?* 2 (0.62) (1.00) (1.64) power-supply voltage: 3.3 v ?0.3 v ta : 0 to 70?* 1 0.60 (0.65) 1.00 (1.00) 1.60 (1.51) use this to multiply the typ. values of t 0 and k at v dd = 3.3 v. power-supply voltage: 3.3 v ?0.3 v ta : -40 to 85?* 2 0.58 (0.62) 1.00 (1.00) 1.67 (1.57) power-supply voltage: 2.0 v ?0.2 v ta : 0 to 70?* 1 0.42 (0.39) 1.00 (1.00) 2.49 (2.94) use this to multiply the typ. values of t 0 and k at v dd = 2.0 v. power-supply voltage: 2.0 v ?0.2 v ta : -40 to 85?* 2 0.42 (0.39) 1.00 (1.00) 2.68 (3.38)
chapter 5: propagation delay time and timing design standard cell S1K50000 series epson 67 design guide 5.3 load due to input capacitance (load a) the delay time in a logic gate depends on the sum total of the input capacitances of the logic gates (fan-in) connected to the output pin of that gate. the input capacitance of each gate (fan-in) and the loading limits of their output pin (fan-out) are listed in the ?tandard cell S1K50000-series msi cell library. in the design of a circuit, make sure the sum total of fan-in will not exceed the output pins fan- out. ?example of the calculation of load a the following shows an example of the calculation of load a using the circuit diagram shown in figure 5-1 and the data given in table 5-2. figure 5-1 circuit for example load-a calculation the fan-in values for kin2, kna2, and kno2 are given in table 5-2. their sum is the value of load a. load a (n1) = ( f an-in of k in2) + ( f an-in of k na2) + (fan-in of k no2) = 2.0 + 1 + 1 = 4.0 table 5-2 data used for example load-a calculation cell input output pin fan-in pin fan-out kin1 a 1.0 x 17.7 kin2 a 2.0 x 36.9 kna2 a1 a2 1.0 1.0 x 15.4 kno2 a1 a2 1.0 1.0 x 8.9 kin 1 kin 2 kna 2 kno 2 2.0 1 1
chapter 5: propagation delay time and timing design 68 epson standard cell S1K50000 series design guide 5.4 load due to wiring capacitance (load b) the load due to the wiring capacitance between cells (load b) is characteristic, in that exact values for it cannot be calculated until placement & routing are actually performed. however, there is a certain correlationship between load b and the number of wiring branches (number of nodes) connected to the outputs of cells, making it possible to statistically predict an assumed value. the assumed wiring capacitance of each master is listed in the ?tandard cell S1K50000-series msi cell library. 5.5 calculating the propagation delay time the following shows an example of the calculation of the propagation delay time using the circuit shown in figure 5-2 (operating at 3.3 v) and the data given in table 5-3. figure 5-2 circuit for example calculation of the propagation delay time table 5-3 characteristics of cells (power-supply voltage of 3.3 v) cell input output t pd (typ.) pin fan-in pin fan-out from to edge t 0 (ps) k (ps/lu) kin1 a 1.0 x 17.7 a x 42 20.9 41 15.0 kin2 a 2.0 x 36.9 a x 32 10.1 32 7.1 kna2 a1 1.0 x 15.4 a1 x 57 20.1 59 25.2 kno 2 a p b c d kin 1 kin 2 kna 2 1 1 2.0
chapter 5: propagation delay time and timing design standard cell S1K50000 series epson 69 design guide here, calculation is performed assuming that load b for node p is 2 [lu]. it should be noted that the nonloaded delay time is added to the propagation delay time, and that the rise and fall of each output must also be taken into conside ration. ? example calculation for paths a ? b, a ? c, a ? d (t pd = typ.) (1) path a ? p : t pd = t pd (kin1) t pd (a ? p ) = t 0 + k (load a + load b) = 41 + 15.0 (4+2) = 131 (ps) t pd (a ? p ) = t 0 + k (load a + load b) = 42 + 20.9 (4+2) = 167.4 (ps) (2) path a ? b : t pd = t pd (kin1) + t pd (kin2) t pd (a ? p ) = t pd (a ? p ) + t pd (p ? b ) = 131.0 + t 0 = 131.0 + 32 = 163 (ps) t pd (a ? p ) = t pd (a ? p ) + t pd (p ? b ) = 167.4 + t 0 = 167.4 + 32 = 199.4 (ps) (3) path a ? c : t pd = t pd (kin1) + t pd (kna2) t pd (a ? c ) = t pd (a ? p ) + t pd (p ? c ) = 131.0 + t 0 = 131.0 + 57 = 188.0 (ps) t pd (a ? c ) = t pd (a ? p ) + t pd (p ? c ) = 167.4 +t 0 = 167.4 + 59 = 226.4 (ps) (4) path a ? d : t pd = t pd (kin1) + t pd (kno2) t pd (a ? d ) = t pd (a ? p ) + t pd (p ? d ) = 131.0 + t 0 = 131.0 + 75 = 206.0 (ps) t pd (a ? d ) = t pd (a ? p ) + t pd (p ? d ) = 167.4 + t 0 = 167.4 + 51 = 218.4 (ps) kno2 a1 1.0 x 8.9 a1 x 75 40.6 51 14.2 table 5-3 characteristics of cells (power-supply voltage of 3.3 v) cell input output t pd (typ.) pin fan-in pin fan-out from to edge t 0 (ps) k (ps/lu)
chapter 5: propagation delay time and timing design 70 epson standard cell S1K50000 series design guide 5.6 calculating the output-buffer delay time letting the load capacitance connected to the output buffer be cl, the delay time tpd is obtained using the equation shown below. t pd = t 0 (output cell) + k (output cell) x c l /10 where t 0 (output cell) : nonloaded delay of output cell [ ps ] k (output cell) : loaded delay coef?ient of output cell [ ps/10 pf ] c l : connected load capacitance [ pf ] for details on the nonloaded and loaded delay coef?ients of output cells, see the ?tandard cell S1K50000-series msi cell library. 5.7 flip-flop setup and hold times the signal timing applied by ?p-?ps and an msi sequential circuit consisting of ?p-?ps play an important role in the proper operation of the con?ured circuit with the intended logic. the ?p-?ps setup and hold times are closely associated with this signal timing. data which, when entered or changed in state, failed to meet the timing requirements regulated by the setup and hold times cannot be written correctly to the ?p-?p circuit. therefore, the signal timing must be designed in consideration of these setup and hold times. (1) minimum pulse width in ?p-?ps and msis consisting of ?p-?ps, this refers to the minimum width of an input pulse between the leading and trailing edges of its waveform. pulses applied in widths smaller than this value are not only ineffective as signals, but may also cause malfunction. the following three minimum pulse widths are de?ed: ?minimum pulse width of a clock signal ?minimum pulse width of a set signal ?minimum pulse width of a reset signal (2) setup time in ?p-?ps and msis consisting of ?p-?ps, if data is to be read correctly, it must be set to the valid state before a change in the active clock edge occurs. the time required for it is referred to as the ?etup time. (3) hold time in ?p-?ps and msis consisting of ?p-?ps, if data is to be read correctly, it should be held in the valid state after the active clock edge is entered. the time required for this is referred to as the ?old time.
chapter 5: propagation delay time and timing design standard cell S1K50000 series epson 71 design guide (4) release time (setup) in ?p-?ps and msis consisting of ?p-?ps, the time before the clock pulse can change state after a set/reset input has been deasserted is referred to as the ?elease time. (5) release time (hold) in ?p-?ps and msis consisting of ?p-?ps, the set/reset input state must be maintained after an active clock pulse is entered. this time is referred to as the ?elease time (hold). (6) set/reset setup time in ?p-?ps and msis consisting of ?p-?ps, the time before a reset input can be asserted after a set input has been deasserted is referred to as the ?et/reset setup time. (7) set/reset hold time in ?p-?ps and msis consisting of ?p-?ps, a reset signal once asserted must be held active until the next time a set signal is asserted. this time is referred to as the ?et/reset hold time. for details on the timing error messages output during simulation, see the users manual of each tool. figure 5-3 kdfsr figure 5-4 timing waveform diagram 1 (explanation diagram for (1) through (5)) set data clock reset q xq d c s r q xq pulse width clock data release (setup) set setup hold release (hold) (reset) set (reset) pulse width pulse width
chapter 5: propagation delay time and timing design 72 epson standard cell S1K50000 series design guide figure 5-5 timing waveform diagram 2 (explanation diagram for (6) through (7)) the ?p-?p setup/hold times of the S1K50000 series are listed in cell libraries in the form shown in table 5-4 below. during actual use, please see the timing characteristics of each individual cell. note: p = transition from 0 to 1 level or positive pulse n = transition from 1 to 0 level or negative pulse table 5-4 timing characteristics of kdfsr (reference) pin setup time (ps) hold time (ps) pulsewidth (ps) ty p. ( v dd = 3.3 v) ty p. ( v dd = 3.3 v) ty p. ( v dd = 3.3 v) c(p) to d 610 291 c(p) to r 367 468 c(p) to s 415 437 r(p) to s(p) 643 c(p) 1022 c(n) 1031 r(n) 991 s(n) 891 reset release (setup) set release (hold) set
chapter 5: propagation delay time and timing design standard cell S1K50000 series epson 73 design guide 5.8 differentiating cell usage (1) cells with names suf?ed by *p, *v, *o, *x2, or *x3 these cells have enhanced drive capability compared to that of ordinary cells. (2) cells with names suf?ed by *c or *x0 these cells have reduced drive capability compared to that of ordinary cells. 5.9 intra-chip skew inside an lsi, due to varying transistor characteristics between lots or makes and other reasons, tpd varies even for the same type of gate. therefore, tpd may have relative drifts between multiple signals. this is known as the ?kew. this skew may make it impossible for the setup or hold time to be met. take this skew into consideration in the design of a circuit, to ensure a suf?ient timing allowance. the intra-chip skews in the S1K50000 series are listed in table 5-5 below. table 5-5 intra-chip skew cell location skew internal cell all areas 5% i/o cell all areas 5%
chapter 6: creating test patterns 74 epson standard cell S1K50000 series design guide chapter 6 creating test patterns upon completion of logic design, create test patterns. not only are test patterns used for simulations to verify operation of the designed circuit, they are also used for product inspection at shipment. to increase the quality of shipped products, note the following in the creation of a test pattern. 6.1 testability consideration because test patterns are used for product inspection at shipment, they must be created so as to allow the entire internal circuit of an lsi to be tested. if any part of the internal circuit of an lsi remains untested, that part cannot be tested at product shipment, which may result in the shipment of ng products. generally speaking, not all parts of the internal circuit of an lsi can be tested. this requires that testability be taken into consideration from the circuit design stage. dc test and various other conditions required for test patterns can be set easily through the insertion of a seiko epson-recommended test circuit. for details, see section 4.4, ?est circuit for functional cells. 6.2 usable waveform modulation a test pattern normally consists of sequences of 0s and 1s. they allow a delay to be inserted in the input waveform or the waveform itself to be altered during a simulation or testing using an lsi tester. the following two waveforms can be used in the creation of a test pattern: ? nrz (non-return to zero) this waveform is normally used for signals other than the clock. this waveform can change state once within a test rate period, making it possible to insert a delay. ? rz (return to zero) this waveform is used primarily for the clock signal. because this waveform can generate a positive or negative pulse within one test rate period, it aids in the ef?ient creation of a clock signal. it also allows a delay to be inserted, as with nrz. figure 6-1 limitations on timing settings test rate output waveform nr rz waveform z waveform strobe input delay pulse width
chapter 6: creating test patterns standard cell S1K50000 series epson 75 design guide 6.3 limitations on test patterns a test pattern set for the actual operating frequency is used for simulation during timing design. because this test pattern is also used for product inspection at shipment, it must be suited for the limitations on lsi testers. observe the limitations described below in the creation of a test pattern. 6.3.1 test rate and the number of events the test rate must be 100 ns or more, in increments of 1 ns (recommended rate: 200 ns). it must also be de?ed in conformity with the limitations described in section 6.3.5, ?trobe. furthermore, lsi testers are subject to limitations on the number of events, which must also be satis?d. number of events per test pattern : up to 256k number of test patterns : up to 30 total number of events in test patterns : up to 1m 6.3.2 input delay (a) range of input delay 0 ns input-delay value < strobe point de?e the input delay within the above range in increments of 1 ns. for the limitations on strobe points, see section 6.3.5, ?trobe. (b) phase difference in input delay 3 ns or more (c) types of input delays within eight types in one test pattern. a 0-ns delay is treated as one type. a delay value in an rz waveform and the same delay value in an nrz waveform are treated as different types. a delay value and the same delay value within an rz waveform or nrz waveform are treated as the same type. 6.3.3 pulse width the pulse width of an rz waveform must be 15 ns or more. 6.3.4 input-waveform format the input waveform can take on the value 0, 1, p, or n. p and n represent pulse inputs in the rz waveform. in addition, p and n can only take on a combination of values, such as (0, p) or (1, n), and no other combinations for the same pin in one test pattern. for bidirectional pins, an rz waveform can only be entered in cases in which the output state is nonexistent. these pins are handled in the same way as for input pins.
chapter 6: creating test patterns 76 epson standard cell S1K50000 series design guide 6.3.5 strobe the strobe-related limitations are as follows: (a) only one type of strobe can be de?ed in each test pattern. (b) the minimum value of a strobe must be such that, under all conditions, the strobe remains active for 30 ns or more after all output signals have had their state changed by an applied input signal. (c) make sure the maximum value of a strobe is smaller than (test rate ?15 ns). (d) set a strobe in increments of 1 ns. 6.4 precautions regarding dc test not only are test patterns used for function tests, they also are used for dc tests in which the output voltage is measured. in the creation of a test pattern, make sure the dc test speci?d below can be performed. a dc test is performed in order to verify the dc parameters of an lsi. therefore, the measured pins cannot change state in a measurement event following strobe input. the following are the items of dc parameters to be measured: (a) output-characteristic test (v oh , v ol ) measure the current drive capability of an output buffer. after setting the measured pins to the intended output level, measure the value of a voltage drop that occurs when a current load stipulated in the speci?ation is applied. in order for an output-characteristic test to be performed, the test pattern must have all states in which the measured pins can operate. in addition, said states cannot change in a measurement event, even when the test rate is extended to in?ity. (b) quiescent-current test (i dds ) ?uiescent current refers to a leakage current that ?ws in the lsi in which inputs are in a steady state. because the amount of this current is generally very small, measurements must be made under conditions in which no currents other than the leakage current are ?wing. to this end, all of the conditions speci?d below must be met. in addition, events in which the quiescent current can be measured must be set at two or more locations.
chapter 6: creating test patterns standard cell S1K50000 series epson 77 design guide (1) all input pins are in a steady state. (2) bidirectional pins are driven high or low, or set for output. (3) no operating parts such as an oscillator exist in the circuit. (4) the internal tri-state buffer (internal bus) is not left ?ating or is not contending for bus control. (5) ram, rom, and megacells are not conducting current. (6) input pins with pull-up resistors are pulled high. (7) bidirectional pins with pull-up resistors are pulled high or are outputting a high signal. (8) bidirectional pins with pull-down resistors are set for input or are outputting a low signal. (c) input-current test measure the input-related parameters of an input buffer. this measurement item includes measurement of the input leakage current and pull-up/pull-down currents. a test is performed for this measurement item through application of the v dd or v ss voltage to the measured pin and measurement of the current ?wing through that pin. this means that a high or low voltage is applied to the measured pin during measurement. if this test is performed by applying the v dd (high) voltage to the measured pin while it is held low, the measured pin changes state from low to high, which may cause the lsi to operate unexpectedly. for measurement during the input-current test, in an event of the test pattern in which the measured pin input is driven high, apply the v dd voltage to the pin. in an event in which the measured pin is held low, apply the v ss voltage to the pin. unless the test pattern has these states for the measured pin, this test cannot be performed. the input-current test is further classi?d into the following categories:
chapter 6: creating test patterns 78 epson standard cell S1K50000 series design guide (1) input-leakage-current test (i ih , i il ) measure the input current-related parameters of an input buffer that does not have a pull-up or pull-down resistor attached. the current that ?ws through the input buffer when a high voltage is applied is referred to as ? ih , and is guaranteed by the maximum current value. for this test to be performed, the test pattern must have an event in which the measured pin has a high signal entered. if the measured pin is a bidirectional pin, it must be set for input, with a high signal entered. the current that ?ws through the input buffer when a low voltage is applied is referred to as ? il , and is guaranteed by the maximum current value. for this test to be performed, the test pattern must have an event in which the measured pin has a low signal entered. if the measured pin is a bidirectional pin, it must be set for input, with a low signal entered. (2) pull-up-current test (i pu ) measure the current that ?ws through the input buffer with a pull-up resistor attached when a low voltage is applied to it. for this test to be performed, the test pattern must have an event in which the measured pin has a low signal entered. if the measured pin is a bidirectional pin, it must be set for input, with a low signal entered. (3) pull-down-current test (i pd ) measure the current that ?ws through the input buffer with a pull-down resistor attached when a high voltage is applied to it. for this test to be performed, the test pattern must have an event in which the measured pin has a high signal entered. if the measured pin is a bidirectional pin, it must be set for input, with a high signal entered. (4) off-state leakage current (i oz ) measure the leakage current that ?ws in an open-drain tri-state output buffer while its outputs are in the hi-z state. this test is actually performed by measuring the current ?wing through the measured pin while in the hi-z state, when the v dd voltage and v ss voltage is applied to it, respectively. therefore, the test pattern must have an event in which the measured pin is placed in the high-impedance state.
chapter 6: creating test patterns standard cell S1K50000 series epson 79 design guide 6.5 precautions on use of an oscillator circuit the following shows examples of oscillator circuits (continuous and intermittent oscillation). figure 6-2 examples of oscillator circuits in general, when an oscillator circuit is used, because the oscillation inverters drive capability is small, and because the oscillator circuits output waveform is affected by the load of the measurement environment, the waveform conveyed to the next stage that follows the oscillator circuit is not exact. to reproduce a simulated state using a tester, therefore, a measure is taken to apply reverse drive (by entering into the drain pin a waveform that is in phase with the signal output to the drain). when the oscillation inverter is structured as inverter, a reverse drive signal can be produced simply by entering a signal for the drain that is opposite in phase to the signal applied to the gate. however, if comprised of a nand gate (known as an ?ntermittent oscillator or ?ated- osc?, the signal to be entered for the drain cannot be determined based on the gate signal alone. for this reason, the reverse-drive waveform is determined based on an expected value for the drain pin. with this method, if the input waveform is an nrz waveform and the strobe exists at the end of the test rate period, the reverse-drive waveform can be produced using the drain pins expected value for the input waveform directly as is. however, in the case of an rz waveform, because the drain pins expected value is ?ed high or low whether oscillating or idle, the reverse-drive waveform cannot be determined based on the drain pins expected value. for an intermittently oscillating circuit, therefore, observe the following: 1. do not use an rz waveform for the input signal. 2. do not change the clock signal by changing the state of the enable signal. gate-side signal drain-side signal clock signal xlin xlot gate-side signal enable signal clock signal xlin oscillator cell oscillator cell drain-side signal xlot g d x g e x d pa d x pa d a pa d x pa d a
chapter 6: creating test patterns 80 epson standard cell S1K50000 series design guide 6.6 regarding the ac test in an ac test, the length of time from when an input pin changes state until that change of state propagates to the output pin is measured. the measurement paths that have been selected by customers are used for the ac test. 6.6.1 restrictions on measurement events this test is normally performed using the method known as ?inary search. therefore, the change points for the measured pin (any output pin that changes state) within a measurement event must be limited to one. (measurement cannot be made of pins that are outputting an rz waveform, nor can measurement be made when a hazard is output in the measurement event.) in addition, changes in state of the measured signal must occur in order of high ? low or low ? high (z-related changes cannot be measured). other precautions include that events must be selected so as not to cause multiple output pins to change state simultaneously in a measurement event, or signal contention to occur between bidirectional pins and the lsi tester. this is due to the fact that a simultaneous change in state or signal contention causes the lsi power supply to swing, affecting the measured pins output waveform and making accurate measurements impossible. 6.6.2 restrictions on ac test measurement points the measurement points in an ac test must be limited to up to four. 6.6.3 restrictions on delays in the measured path with the ac test measurement paths, the greater the delay in the measured path, the higher the accuracy of measurement. make sure the delay time in the measured path is set to 30 ns or more, and is equal to or less than the strobe point under maximum test simulation conditions. 6.6.4 other restrictions (1) do not specify a path from the oscillator circuit. (2) make sure the speci?d path does not pass through the internal tri-state circuit (internal bus). (3) do not specify a path that passes through any other bidirectional cell between the measured paths input buffer and the output buffer. (4) if there are two or more working voltage ranges, make sure the measured voltages in the ac test are both within one of such voltage ranges.
chapter 6: creating test patterns standard cell S1K50000 series epson 81 design guide 6.7 restrictions on test patterns for bidirectional pins due to tester limitations, bidirectional pins cannot be switched between input and output modes more than twice within one event. therefore, in the creation of a test pattern, make sure it will not use rz waveforms to control switching between the input and output modes of a bidirectional cell. for bidirectional pins, however, rz waveforms can be used, provided that the pin does not have an output state and is handled in the same way as an input pin. 6.8 precautions on handling of the high-impedance state at seiko epson, the input pins of cmos devices cannot be in the high-impedance state during simulation, as device operation cannot be guaranteed. for high-impedance-related measures, i/o cells with pull-up/down resistors are available from seiko epson. however, for the reasons speci?d below, propagation delays during simulation are not taken into consideration for changes in signal state due to the pull-up/down resistors. because exact operation cannot be simulated, for i/o cells with pull-up/down resistors (including bidirectional pins), a non-input state cannot exist in the input mode during simulation. ? because the delay ?ctuates signi?antly due to the external load capacitance ? because the pull-up/down resistors are used only to avoid ?ating gates caused by the high-impedance state at seiko epson, before simulation is performed, test patterns are checked for the above using a tool. when the letter ?, which represents the high-impedance state, is detected in bidirectional pins (including those with n-channel open-drain output), customers are requested to correct the test pattern. in such a case, if the letter ? is detected in bidirectional pins with pull-up/down resistors, customers will also be requested to correct the test pattern for the reasons described above. the same applies to bidirectional pins with open-drain output.
chapter 6: creating test patterns 82 epson standard cell S1K50000 series design guide when test patterns are checked, all occurrences of ? in bidirectional pins are indicated by the generation of an error (this does not include the ? that is used in the expression of tri-state and n-channel open-drain output pins). as a means of correcting input patterns, seiko epson uses a utility program that automatically replaces the ? in said bidirectional pins with logic ? if they have a pull-up resistor, or with logic ? if they have a pull-down resistor. for bidirectional pins, if a pin containing the letter ? is set for the input mode, the ? is propagated in simulation. in the simulation result, it is expressed as ?, regardless of whether the pin comes with a pull-up/down resistor. customers are requested to correct the input pattern for occurrences of ? before seiko epson reexecutes simulation. table 6-1 handling of bidirectional-pin signals in simulation input pattern input/output mode simulation simulation result (output pattern) ? input mode ? ? ?? ? input mode ? ? ?? ? input mode ? ?
chapter 7: estimating power consumption standard cell S1K50000 series epson 83 design guide chapter 7 estimating power consumption in cmos lsis, virtually no current ?ws through the chip while it is idle. during operation, however, they consume a certain amount of power in proportion to the operating frequency. as the power consumption increases, so does the temperature of the lsi chip. an excessively high chip temperature adversely affects the lsi quality, making it necessary to calculate the chips power consumption in order to determine whether the power consumption falls within its rated power dissipation. 7.1 calculating power consumption power consumption in cmos circuits generally depends on the circuits operating frequency, load capacitance, and power-supply voltage (this does not include special circuits such as ram and rom through which a steady current is ?wing). consequently, the power consumption in cmos gate arrays can be calculated easily only if the operating frequency and load capacitance of each cell used in the circuit are known. because the load capacitance of internal cells is dif?ult to calculate for each cell, the approximate calculation described below may be used. when making this calculation, determine the power consumption in each of the input and output buffers and internal cells. the sum total of the foregoing is the chips total power consumption. therefore, the total power consumption to be calculated, p total , is expressed by the equation shown below. p i : power consumption in the input buffer p total = p i + p o + p int p o : power consumption in the output buffer p int : power consumption in the internal cell to calculate the power consumption in a dual-power-supply system, see chapter 9, ?recautions on the use of dual power supplies.
chapter 7: estimating power consumption 84 epson standard cell S1K50000 series design guide (1) power consumption in input buffers (p i ) the power consumption in input buffers is the sum total of the signal frequencies entered in each buffer (mhz) multiplied by kp i (?/mhz). k p i = (kp i f i ) (w) i=1 where kp i : power factor of the input buffer (?/mhz). see table 7-1 below. varies with the operating voltage. f i : operating frequency of the i ?h input buffer (mhz) (2) power consumption of output buffers (p o ) the power consumption of output buffers differs between dc loads (resistive loads, such as when the counterpart to be connected to is a ttl device) and ac loads (capacitive loads, such as when the counterpart to be connected to is a cmos device). in the case of an ac load, the power consumption can be obtained based on the load capacitance cl in the following manner: ? ac power consumption p ac = f c l (v dd ) 2 (w) where f : operating frequency of the output buffer (hz) c l : load capacitance (f) v dd : power-supply voltage (v) in the case of a dc load, the power consumption consists of the amount of power consumed by a dc load plus the ac power consumption. table 7-1 input cell kpi in the S1K50000 series v dd (typ.) kp i 3.3 v 6.2 ?/mhz 2.0 v 2.0 ?/mhz
chapter 7: estimating power consumption standard cell S1K50000 series epson 85 design guide ? dc power consumption p dc = p dch + p dcl where p dch = | i oh | (v dd - v oh ) (w) p dcl = i ol v ol (w) the p dch -to-p dcl ratio is determined by the duty cycle of the output signal. figure 7-1 typical duty cycle duty h = (t 1 + t 2 ) / t duty l = (t - t 1 - t 2 ) / t therefore, p dc = p dch + p dcl kk = {(v dd - v oh i ) i oh i duty h } + {v ol i i ol i duty l} i=1 i=1 thus, the power consumption (po) of the output buffer is p o = (p ac + p dc ) kk = {f i c l i (v dd ) 2 } + {(v dd - v oh i ) i oh i duty h } i=1 i=1 k + { v ol i i ol i duty l } i=1 t t 1 t 2
chapter 7: estimating power consumption 86 epson standard cell S1K50000 series design guide (3) power consumption in the internal cells (p int ) the power consumption in the internal cells varies depending on the cell type, usage ef?iency of the cell, operating frequency, and the percentage of cells that operate at that operating frequency, and is calculated as follows: k p int = {n f i s p i (k pint )} (w) i=1 where n : total number of bc f i : operating frequency of the i?h cell (mhz) s p i : percentage of cells among all that operate at the operating frequency, f i (approximately 20%?0% is recommended) k pint : see table 7-2 to provide low-power operation, seiko epson offers a low-power-consumption-type cell known as a ?ow-power cell. use of this low-power cell helps to reduce the power consumption per gate to almost half that of ordinary cells (normal cell), although the propagation delay time increases slightly. when using low-power cells, halve the S1K50000-series k pint value per bc listed in table 7-2 in the calculation of the power consumption. the low-power cells are ?p-?p cells with names suf?ed by ?0, and cells with names suf?ed by ?. table 7-2 k pint per bc in the S1K50000 series v dd (typ.) k pint 3.3 v 0.22 ?/mhz 2.0 v 0.08 ?/mhz
chapter 7: estimating power consumption standard cell S1K50000 series epson 87 design guide 7.2 limitations on power consumption the chip temperature of lsis increases in proportion to their power consumption. the chip temperature of a package-mounted lsi can be calculated based on its ambient temperature ta, the packages thermal resistance q, and power dissipation pd. chip temperature (tj) = ta + (pd ) (?) under normal operating conditions, we recommend using lsis at a chip temperature (tj) of approximately 125? or less. the thermal resistance of each package is listed in table 7-3. the thermal resistance of packages, as shown in table 7-3, ?ctuates signi?antly depending on how the chip is mounted on the board and whether the chip is heat-radiated by a fan. table 7-3 thermal resistance of each package (single unit in a suspended state) qfp5 qfp5 qfp8 qfp8 qfp12 qfp13 qfp14 qfp15 tqfp14 tqfp14 tqfp15 pin 100 128 128 208 48 64 80 100 80 100 100 110 ( 50 60 60 45 55 55 35 qfp20 144 85 70 50 40 qfp5 qfp5 qfp5 qfp8 qfp8 qfp10 qfp12 qfp13 qfp14 qfp15 qfp20 qfp21 qfp21 qfp22 qfp22 qfp23 qfp23 tqfp12 tqfp13 tqfp15 tqfp24 hqfp5 h2qfp23 h3qfp15 80 100 128 160 256 304 48 64 80 100 184 176 216 208 256 184 240 48 64 128 144 128 240 128 85( 20 120 80 35 35 45 35 35 25 16 90 55 25 25 40 30 30 23 80 50 23 23 hqfp8 160 32 19 12 10 h2qfp8 208 34 pbga pbga pbga 225 256 388 72( 37 25 9.55 mm
chapter 8: pin arrangement and simultaneous operation 88 epson standard cell S1K50000 series design guide chapter 8 pin arrangement and simultaneous operation 8.1 estimating the number of power-supply pins the necessary number of power-supply pins must be estimated based on the lsis power consumption and the number of output buffers. in particular, the output buffers conduct a large amount of transient current when switched. this transient current tends to increase as the output buffers drive capability increases. regarding the number of power-supply pins required for the lsi, the following applies with respect to current consumption. letting the current consumption be i dd [ma], the number of power-supply pins in pairs, n idd , required for this current consumption, i dd , is expressed by the equation shown below. n idd i dd /50 (pair); 50 ma per pair of pins can be supplied note: the number of power-supply pins in pairs, n idd , must at least be two pairs or more. i dd is the power consumption obtained in chapter 7 divided by the operating voltage. for details on how to estimate the number of power-supply pins in a dual-power-supply system, see chapter 9, ?recautions on the use of dual power supplies. note: if the output buffers have a dc load connected and a steadily ?wing current, one or more power-supply pins must be added. for more information, contact seiko epson or its distributor. 8.2 simultaneously operating buffers and added power supply the S1K50000-series cells have a large output drive capability of up to 12 ma. as a result, the output buffers generate a large amount of noise during operation, and an extremely large amount during simultaneous operation. if a large number of output buffers are operated simultaneously in your application, add power supplies to prevent noise-induced malfunction, as shown in tables 8-1-1 through 8- 2-2.
chapter 8: pin arrangement and simultaneous operation standard cell S1K50000 series epson 89 design guide table 8-1 number of v ss power supplies added for simultaneous operation of output buffers (v dd = 3.3 v) output drive capability (i ol ) number of buffers operating simultaneously number of power supplies to add c l 50 pf c l 100 pf c l 200 pf 6 ma 8012 16 1 2 3 24 1 2 4 32 2 3 5 12 ma 8122 16 2 2 3 24 2 3 5 32 2 4 8 pci 8123 16 2 3 4 24 3 4 5 32 4 5 10 table 8-2 number of v ss power supplies added for simultaneous operation of output buffers (v dd = 2.0 v) output drive capability (i ol ) number of buffers operating simultaneously number of power supplies to add c l 50 pf c l 100 pf c l 200 pf 4 ma 8012 16 1 2 3 24 1 2 4 32 2 3 5
chapter 8: pin arrangement and simultaneous operation 90 epson standard cell S1K50000 series design guide table 8-3 number of v dd power supplies added for simultaneous operation of output buffers (v dd = 3.3 v) output drive capability (i oh ) number of buffers operating simultaneously number of power supplies to add c l 50 pf c l 100 pf c l 200 pf 6 ma 8011 16 1 1 2 24 1 2 3 32 1 2 3 12 ma & pci 8122 16 2 2 3 24 2 3 3 32 3 3 6 table 8-4 number of v dd power supplies added for simultaneous operation of output buffers (v dd = 2.0 v) output drive capability (i oh ) number of buffers operating simultaneously number of power supplies to add c l 50 pf c l 100 pf c l 200 pf 4 ma 8011 16 1 1 2 24 1 2 3 32 1 2 3
chapter 8: pin arrangement and simultaneous operation standard cell S1K50000 series epson 91 design guide 8.3 precautions on pin arrangement when it is decided which package to use, determine the pin arrangement on the package. for the power-supply pins and the number of usable input/output pins on each package of the S1K50000 series, refer to the designated ?in arrangement table. when the pin arrangement is decided, send a ?in arrangement table to seiko epson after specifying the pin arrangement on the designated sheets. at seiko epson, placement & routing is performed based on the presented ?in arrangement table, so be sure to con?m that there are no errors or omissions in the table before sending it. to obtain the designated form for the ?in arrangement table, contact seiko epson or its distributor. the pin arrangement is one important speci?ation that determines the quality of lsi. it is particularly important in terms of preventing noise-induced malfunction. this is even more important when the dif?ulty of identifying such noise through simulation or the like is taken into consideration. to prevent malfunctions in customers lsis due to unknown causes, we recommend carefully reading the contents hereof before creating a pin arrangement table. 8.3.1 fixed power-supply pins depending on the combination of cell types and the package in this series, some pins can only be used for the power supply. in addition, some pins must be ?ed to v dd , while others must be ?ed to v ss. when selecting a package, con?m this method of pin ?ation by referring to the ?in arrangement table. 8.3.2 precautions on pin arrangement the pin arrangement affects the lsis logic functions and electrical characteristics. furthermore, the pin arrangement is subject to limitations for reasons involving lsi assembly, the cell, or the bulk structure. therefore, the following explains the factors requiring caution in the examination of pin arrangement. these factors include the power-supply current, separation of input and output pins, critical signals, simultaneous input/output changes in pull- up/down resistors, and large-current drivers.
chapter 8: pin arrangement and simultaneous operation 92 epson standard cell S1K50000 series design guide (1) power-supply currents (i dd , i ss ) power-supply currents (i dd , i ss ) stipulate the rated amount of current that is allowed to ?w through the power-supply pins during operation. if a current exceeding this allowable level ?ws, the current density in the lsis internal power-supply wiring becomes excessively high, causing the lsis reliability to degrade or the device itself to break down. in addition, the lsis internal voltage increases or decreases by the amount of voltage generated by the current and wiring resistance. this results in device malfunction or adversely affects the dc and ac characteristics. to prevent such problems, the current density and the impedance of the power-supply wiring must be reduced. this can be accomplished by estimating the power consumption of standard cells in the design of a circuit, and then preparing a suf?ient number of power- supply pins so that the current ?wing through each power-supply pin does not exceed the permissible value. for details, see section 8.1, ?stimating the number of power-supply pins. in addition, make sure the power-supply pins are placed so as to be separated from each other. note, however, that the number of power-supply pins ?ally required is not simply the number of supply pins calculated above, but also includes the power-supply pins that are added as a means of preventing noise problems. for details on the number of supply pins added, see section 8.2, ?imultaneously operating buffers and added power supply. (2) noise generated by the operation of output cells the noise generated by the operation of output cells can be broadly classi?d into the two types speci?d below. to reduce these types of noise, install as many power supplies as possible. a) noise generated in power-supply lines the noise generated in power-supply lines presents a problem when multiple outputs are activated, causing the lsis input threshold level to change, which in turn causes malfunction. the noise in power-supply lines is generated by the simultaneous operation of output cells, which causes a large current to ?w through the power-supply lines. the power-supply noise is affected by inductance components. therefore, an lsis equivalent circuit can be expressed as shown in figure 8-1. in this circuit diagram, when the output changes state from high to low, a current ?ws from the output pin into the lsis internal logic, with the current ?wing through the equivalent inductance l2 due to the lsis package or the like. at this time, the equivalent inductance l2 causes the voltage in the lsis internal v ss power-supply line to ?ctuate. this voltage ?ctuation in the v ss power- supply line is the ?oise generated in power-supply lines. because this noise is generated primarily by the equivalent inductance l2, the greater the rapidity of the power-supply current, the larger the amount of noise generated.
chapter 8: pin arrangement and simultaneous operation standard cell S1K50000 series epson 93 design guide figure 8-1 equivalent circuit of an lsi b) overshoot, undershoot, and ringing some types of noise, known as overshoot, undershoot, and ringing, are generated by the equivalent inductance inherent in output pins. this equivalent inductance is represented by l3 in figure 8-1. because inductance tends to accumulate energy, even when the output changes state to low or high, the accumulated energy generates an overshoot, undershoot, or ringing. therefore, overshoot and undershoot are proportionate to the magnitude of ?wing current, and also to the change rate of the current. the most ef?ient means of reducing overshoot and undershoot is the use of output cells with a small drive capability. as the load capacitance increases, overshoot and undershoot tend to decrease. therefore, caution is required, particularly when output cells with a large drive capability are used. input pin v 1 l 2 l 3 v dd (internal) v ss (internal) l 1 v dd output pin
chapter 8: pin arrangement and simultaneous operation 94 epson standard cell S1K50000 series design guide (3) separating input and output pins for pin arrangement, it is an important technique to separate input-pin groups from output- pin groups, as this helps to reduce the in?ence of noise. input pins and bidirectional pins set for input are susceptible to noise. it is therefore important that these pins do not coexist with output pins. to this end, place input pins, output pins, and bidirectional pins so that they are separated from each other, with power- supply pins placed between each group of pins to divide them. figure 8-2 example of the separation of input and output pins (4) critical signals when placing critical signals issued from such output pins as clock-input and fast-operating output pins, observe the following precautions: a) place the clock and reset pins that require minimization of the in?ence of noise away from output pins and close to the power-supply pins (figure 8-3). b) place the oscillator circuits input/output pins (oscin, oscout) close to each other, separated from other pins by the power-supply pins (v dd , v ss ). do not place output pins that are synchronous to the oscillator circuit near said pins (figure 8-4). c) place fast-operating input and output pins near the middle of one side of the chip (package) (figure 8-3). d) if the delay time from any speci? input pin to an output pin has a small margin in the customer speci?ations, place these input/output pins close to each other (figure 8-3). figure 8-3 example of the placement of critical signal pins ?1 v dd v ss v ss v dd v dd v ss v ss v dd v dd v ss v dd v ss output pins input pins output pins bid pins high speed input through input through output rst v ss v ss clk high speed output
chapter 8: pin arrangement and simultaneous operation standard cell S1K50000 series epson 95 design guide figure 8-4 example of the placement of critical signal pins ?2 (5) pull-up/pull-down resistor inputs pull-up/pull-down resistors have rather large resistance values ranging from several 10 kohms to several 100 kohms and, due to their structure, they are dependent on the power- supply voltage. if these resistors are used, for example, as test pins while being left open, they tend to be affected easily by power-supply noise and the like to become a cause of malfunction. therefore, observe the following precautions when placing these resistors: a) place the pull-up/pull-down resistors as far from the fast input-signal pins (e.g., clock input pin) as possible (figure 8-5). b) place the pull-up/pull-down resistors so that they are separated from the output-signal pins (particularly large-current output pins) (figure 8-6). in addition to the above pin-placement precautions, also take the following into account: apply pull-up/pull-down processing to the board (pcb) as much as possible. choose pull-up/pull-down resistors with resistance values as small as possible. figure 8-5 example of the placement of pull-up/pull-down pins ?1 figure 8-6 example of the placement of pull-up/pull-down pins ?2 v ss oscin v dd oscout v ss clk pull up pull down high drive output
chapter 8: pin arrangement and simultaneous operation 96 epson standard cell S1K50000 series design guide (6) simultaneous change in outputs if multiple pins change state simultaneously, they generate noise, causing the lsi to operate erratically. if it is necessary to operate a large number of output pins simultaneously, add power-supply pins to a group of output pins that change state simultaneously in order to prevent such a noise-induced malfunction. for details on the number of power-supply pins to add, as well as the placement method for those additional power-supply pins, see section 8.2, ?imultaneously operating buffers and added power supply. one method of reducing said noise is to insert a cell that causes a delay in front of one group of output cells. this helps to reduce the number of output pins that change state simultaneously and therefore the noise generated by a simultaneous change in state (figure 8-8). simultaneously changing output pins figure 8-7 example of the addition of power-supply pins figure 8-8 example of the addition of a delay cell (7) large-current drivers when using the output of large-current drivers (i ol = 12 ma, 24 ma, pci), observe the restrictions described below in the placement of these pins. a) restrictions on power-supply enhancement because large-current drivers have a large drive capability, the amount of noise generated by the output buffers when they operate is also large. this noise may cause the lsi to operate erratically. when using large-current drivers, place power-supply pins near their pins to secure the power supply needed for such drivers (figure 8-9). v dd v ss v ss v dd v ss v ss v v dd a out1 xob3t a out2 xob3t ta ts ta ts dl1
chapter 8: pin arrangement and simultaneous operation standard cell S1K50000 series epson 97 design guide b) low-noise predrivers to reduce the amount of noise generated by the output buffers of large-current drivers during operation, special low-noise output and bidirectional buffers available from seiko epson may be used. for details, see chapter 3, ?ypes of input/output buffers and usage precautions. figure 8-9 example of power-supply enhancement (8) other precautions the relationship between the package pins and lsi pads is predetermined based on the combination of product types and packages in each series. therefore, pin usage may be subject to limitations due to the package, or pin placement may be subject to limitations due to the input/output buffer types. consider the precautions described below before determining the pin arrangement. a) nc (non-connected) pins if the number of lsi pads is smaller than the number of package pins or the lsi pads cannot be assembled into the package pins, some package pins cannot be used. these pins are indicated by ?* in the pin arrangement table. b) tab suspended pins the tab suspended pins are the package pins that are connected directly to the lsi substrate. these pins are at the v ss (gnd) level without being supplied with power from external sources. normally, leave these pins open when they are mounted on the board. these pins are indicated by ?# in the pin arrangement table. v ss v ss high drive output
chapter 8: pin arrangement and simultaneous operation 98 epson standard cell S1K50000 series design guide 8.3.3 example of the recommended pin arrangement pin layout is an important factor in determining whether the lsi will operate correctly. the following shows an example of pin arrangement (figure 8-10) that takes into account all that has been explained in this chapter. refer to this example in determining the pin arrangement of your application. figure 8-10 example of recommended pin arrangement input pins are placed on the upper and left sides of the package, while output pins that change state simultaneously are placed on the right side. bidirectional pins and other output pins are placed on the lower side. v dd plup inp 9 inp 10 inp 11 inp 12 inp 13 clk v ss inp 14 inp 15 inp 16 inp 17 inp 18 inp 19 v dd v ss sout 0 sout 1 sout 2 sout 3 sout 4 v dd sout 5 sout 6 sout 7 sout 8 sout 9 v ss inp 8 inp 7 inp 6 inp 5 v ss oscin v dd oscout v ss inp 4 inp 3 inp 2 inp 1 inp 0 v ss v dd v ss bid 0 bid 1 bid 2 bid 3 bid 4 hout out 0 out 1 mosc v dd input pins output pins input pins bid pins output pins v dd v ss v ss v ss v ss v ss v ss v ss
chapter 8: pin arrangement and simultaneous operation standard cell S1K50000 series epson 99 design guide table 8-5 explanation of example pin arrangement location pin name explanation of pin name detailed explanation of the position of each pin upper edge pulp clk input pins with pull ups input pins for the clock located where the impact of noise is the least. located near the center of the package, and near power supply pins. left edge oscin,oscout inp0 to19 oscillator pins input pins located near the center of the package, and near power supply pins. located with power supply pins, away from other pins. right-hand edge sout0 to 9 simultaneously changing output pins located near power supply pins and separated from other pins with additional power supply pins. bottom edge bid0 to 4 mosc hout out01 bi-directional pins oscillator monitor output pins high-drive output pins output pins located near power supply pins and separated from other pins. located separated from oscillator pins and near power supply pins. located near power supply pins. located near power supply pins and separated from other pins. all edges v dd v ss v dd power supply pins v ss (gnd) power supply pins
chapter 9: precautions on the use of dual power supplies 100 epson standard cell S1K50000 series design guide chapter 9 precautions on the use of dual power supplies the S1K50000 series supports a dual-power-supply system (5.0 v and 3.3 v, or 3.3 v and 2.0 v), allowing input/output buffers to be individually interfaced with a signal of 5.0 v, 3.3 v, or 2.0 v. the internal cell area operates with a single power supply of 3.3 v or 2.0 v. 9.1 power-supply accommodation the S1K50000 series allows signals operating at voltages that differ from the internal operating voltage to be interfaced. the following two methods can be used to interface with different power-supply systems: ? for a single power supply for a single power supply, signals with voltages higher than the power-supply voltage can be fed into the chip through the use of n-channel open-drain buffers or fail-safe cells. however, signals with higher voltages than the power-supply voltage cannot be output from the chip. in such a case, the n-channel open-drain buffers and external pull-up resistors can be used in combination. ? for dual power supplies signals with higher voltages than the power-supply voltage can be fed into the chip through the use of dedicated dual-power-supply input buffers. similarly, signals with higher voltages than the power-supply voltage cannot be output from the chip through the use of dedicated dual-power-supply output buffers.
chapter 9: precautions on the use of dual power supplies standard cell S1K50000 series epson 101 design guide 9.2 power supplies in a dual-power-supply system to apply two different power supplies, use two power-supply cells: hv dd and lv dd . use hv dd as the power supply for the hv dd system input/output buffers, and lv dd as the power supply for the lv dd system input/output buffers and internal cells. these two power-supply voltages must always meet the following requirement: hv dd lv dd if hv dd < lv dd , device operation cannot be guaranteed. the following two operating conditions are recommended: ?hv dd = 5.0 v, lv dd = 3.3 v ?hv dd = 3.3 v, lv dd = 2.0 v S1K50000-series usage example with two power supplies figure 9-1 S1K50000-series usage example with two power supplies 9.3 dual-power-supply-type input/output buffers when operating with a dual-power-supply system, use dedicated dual-power-supply input/ output buffers. be aware that single-power-supply input/output buffers cannot be used in a dual-power-supply system. therefore, single-power-supply input/output buffers cannot be used in combination with dedicated dual-power-supply input/output buffers. an exception is the test-use buffer (xitst1), which can be used for both dual- and single-power-supply systems. ic operating at 5.0 v ic operating at 3.3 v S1K50000 series 3.3 v 5.0 v 3.3 v internal operating voltage
chapter 9: precautions on the use of dual power supplies 102 epson standard cell S1K50000 series design guide 9.3.1 lv dd -system input/output buffers the lv dd -system input/output buffers are available in several types, including an input buffer that accepts the input of 3.3 v (or 2.0 v) signals, an output buffer that outputs 3.3-v (or 2.0-v) amplitude signals, and a bidirectional buffer that accepts the input of 3.3-v (or 2.0-v) signals and outputs 3.3-v (or 2.0-v) amplitude signals. the lv dd -system input buffers cannot accept hv dd -system signals, because if such a high-voltage signal is fed in, an excessive current ?ws into the internal protective diode of the lv dd -system buffer, causing its quality to degrade. therefore, do not apply voltages higher than lv dd . 9.3.1.1 lv dd -system input buffers this input buffer consists only of input cells. several types of lv dd -system input buffers are available, as listed in tables 9-1-1 and 9-1-2. note: when ? value is 1 or 2, the pull-up/pull-down resistance values correspond to 1:50 k ? , 2:100 k ? respectively. note: when ? value is 1 or 2, the pull-up/pull-down resistance values correspond to 1:120 k ? , 2:240 k ? respectively. table 9-1-1 lv dd -system input buffers (lv dd = 3.3 v) cell name input level fuction with or without a pull-up/down resistor xlibc xlibcp ? xlibcd ? lvttl lvttl lvttl buffer buffer buffer without pull-up resistor (50 k ? , 100 k ? ) pull-down resistor (50 k ? , 100 k ? ) xlibh xlibhp ? xlibhd ? lvttl schmitt lvttl schmitt lvttl schmitt buffer buffer buffer without pull-up resistor (50 k ? , 100 k ? ) pull-down resistor (50 k ? , 100 k ? ) xlibpb xlibpbp ? xlibpbd ? pci-3v pci-3v pci-3v buffer buffer buffer without pull-up resistor (50 k ? , 100 k ? ) pull-down resistor (50 k ? , 100 k ? ) table 9-1-2 lv dd -system input buffers (lv dd = 2.0 v) cell name input level fuction with or without a pull-up/down resistor xlibc xlibcp ? xlibcd ? cmos cmos cmos buffer buffer buffer without pull-up resistor (120 k ? , 240 k ? ) pull-down resistor (120 k ? , 240 k ? ) xlibh xlibhp ? xlibhd ? cmos schmitt cmos schmitt cmos schmitt buffer buffer buffer without pull-up resistor (120 k ? , 240 k ? ) pull-down resistor (120 k ? , 240 k ? )
chapter 9: precautions on the use of dual power supplies standard cell S1K50000 series epson 103 design guide 9.3.1.2 lv dd -system output buffers the available types of S1K50000-series lv dd -system output buffers are listed in tables 9-2-1 and 9-2-2. notes * v ol = 0.4 v (lv dd = 3.3 v) ** v oh = lv dd - 0.4 v (lv dd = 3.3 v) *** in addition to the output buffers listed in table 9-2-1, a configuration without test pins may be considered. if such a configuration is desired, contact seiko epson or its distributor. table 9-2-1 lv dd -system output buffers (lv dd = 3.3 v) function i ol * / i oh ** cell name *** normal output 0.1 ma / -0.1 ma 1 ma / -1 ma 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xlobst xlobmt xlob1t xlob2t xlob3t output for pci pci-3v xlobpbt normal output for high speed 12 ma / -12 ma xlob3at normal output for low noise 12 ma / -12 ma xlob3bt 3-state output 0.1 ma / -0.1 ma 1 ma / -1 ma 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xltbst xltbmt xltb1t xltb2t xltb3t 3-state output for pci pci-3v xltbpbt 3-state output for high speed 12 ma / -12 ma xltb3at 3-state output for low noise 12 ma / -12 ma xltb3bt 3-state output for (bus hold circuit) 1 ma / -1 ma 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xltbmht xltb1ht xltb2ht xltb3ht 3-state output for high speed (bus hold circuit) 12 ma / -12 ma xltb3aht 3-state output for low noise (bus hold circuit) 12 ma / -12 ma xltb3bht
chapter 9: precautions on the use of dual power supplies 104 epson standard cell S1K50000 series design guide notes * v ol = 0.2 v (lv dd = 2.0 v) ** v oh = lv dd - 0.2 v (lv dd = 2.0 v) *** in addition to the output buffers listed in table 9-2-2, a configuration without test pins may be considered. if such a configuration is desired, contact seiko epson or its distributor. table 9-2-2 lv dd -system output buffers (lv dd = 2.0 v) function i ol * / i oh ** cell name*** normal output 0.05 ma / -0.05 ma 0.3 ma / -0.3 ma 0.6 ma / -0.6 ma 2 ma / -2 ma 4 ma / -4 ma xlobst xlobmt xlob1t xlob2t xlob3t normal output for high speed 4 ma / -4 ma xlob3at normal output for low noise 4 ma / -4 ma xlob3bt 3-state output 0.05 ma / -0.05 ma 0.3 ma / -0.3 ma 0.6 ma / -0.6 ma 2 ma / -2 ma 4 ma / -4 ma xltbst xltbmt xltb1t xltb2t xltb3t 3-state output for high speed 4 ma / -4 ma xltb3at 3-state output for low noise 4 ma / -4 ma xltb3bt 3-state output for (bus hold circuit) 0.3 ma / -0.3 ma 0.6 ma / -0.6 ma 2 ma / -2 ma 4 ma / -4 ma xltbmht xltb1ht xltb2ht xltb3ht 3-state output for high speed (bus hold circuit) 4 ma / -4 ma xltb3aht 3-state output for low noise (bus hold circuit) 4 ma / -4 ma xltb3bht
chapter 9: precautions on the use of dual power supplies standard cell S1K50000 series epson 105 design guide 9.3.1.3 lv dd -system bidirectional buffers the available types of S1K50000-series lv dd -system bidirectional buffers are listed in tables 9-3-1 and 9-3-2. notes * v ol = 0.4 v (lv dd = 3.3 v) ** v oh = lv dd - 0.4 v (lv dd = 3.3 v) *** in addition to the bidirectional buffers listed in table 9-3-1, a configuration with pull-up/pull-down resistors or without test pins may be considered. if such a configuration is desired, contact seiko epson or its distributor. table 9-3-1 lv dd -system bidirectional buffers (lv dd = 3.3 v) input level function i ol * / i oh ** cell name lvttl bi-directional output 0.1 ma / -0.1 ma 1 ma / -1 ma 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xlbcst xlbcmt xlbc1t xlbc2t xlbc3t bi-directional output for high speed 12 ma / -12 ma xlbc3at bi-directional output for low noise 12 ma / -12 ma xlbc3bt pci bi-directional output for pci pci-3v xlbpbt lvttl schmitt bi-directional for low noise output 0.1 ma / -0.1 ma 1 ma / -1 ma 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xlbhst xlbhmt xlbh1t xlbh2t xlbh3t bi-directional output for high speed 12 ma / -12 ma xlbh3at bi-directional output for low noise 12 ma / -12 ma xlbh3bt lvttl bi-directional output (bus hold circuit) 1 ma / -1 ma 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xlbcmht xlbc1ht xlbc2ht xlbc3ht bi-directional output for high speed (bus hold circuit) 12 ma / -12 ma xlbc3aht bi-directional output for low noise (bus hold circuit) 12 ma / -12 ma xlbc3bht lvttl schmitt bi-directional output (bus hold circuit) 1 ma / -1 ma 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xlbhmht xlbh1ht xlbh2ht xlbh3ht bi-directional output for high speed (bus hold circuit) 12 ma / -12 ma xlbh3aht bi-directional output for low noise (bus hold circuit) 12 ma / -12 ma xlbh3bht
chapter 9: precautions on the use of dual power supplies 106 epson standard cell S1K50000 series design guide notes * v ol = 0.2 v (lv dd = 2.0 v) ** v oh = lv dd - 0.2 v (lv dd = 2.0 v) *** in addition to the bidirectional buffers listed in table 9-3-2, a configuration with pull-up/pull-down resistors or without test pins may be considered. if such a configuration is desired, contact seiko epson or its distributor. table 9-3-2 lv dd -system bidirectional buffers (lv dd = 2.0 v) input level function i ol * / i oh ** cell name cmos bi-directional output 0.05 ma / -0.05 ma 0.3 ma / -0.3 ma 0.6 ma / -0.6 ma 2 ma / -2 ma 4 ma / -4 ma xlbcst xlbcmt xlbc1t xlbc2t xlbc3t bi-directional output for high speed 4 ma / -4 ma xlbc3at bi-directional output for low noise 4 ma / -4 ma xlbc3bt cmos schmitt bi-directional for low noise output 0.05 ma / -0.05 ma 0.3 ma / -0.3 ma 0.6 ma / -0.6 ma 2 ma / -2 ma 4 ma / -4 ma xlbhst xlbhmt xlbh1t xlbh2t xlbh3t bi-directional output for high speed 4 ma / -4 ma xlbh3at bi-directional output for low noise 4 ma / -4 ma xlbh3bt cmos bi-directional output (bus hold circuit) 0.3 ma / -0.3 ma 0.6 ma / -0.6 ma 2 ma / -2 ma 4 ma / -4 ma xlbcmht xlbc1ht xlbc2ht xlbc3ht bi-directional output for high speed (bus hold circuit) 4 ma / -4 ma xlbc3aht bi-directional output for low noise (bus hold circuit) 4 ma / -4 ma xlbc3bht cmos schmitt bi-directional output (bus hold circuit) 0.3 ma / -0.3 ma 0.6 ma / -0.6 ma 2 ma / -2 ma 4 ma / -4 ma xlbhmht xlbh1ht xlbh2ht xlbh3ht bi-directional output for high speed (bus hold circuit) 4 ma / -4 ma xlbh3aht bi-directional output for low noise (bus hold circuit) 4 ma / -4 ma xlbh3bht
chapter 9: precautions on the use of dual power supplies standard cell S1K50000 series epson 107 design guide 9.3.2 lv dd -system fail-safe cells ? fail-safe input buffers note * the indicated resistance values are for lv dd = 3.3 v. ? fail-safe output buffers notes * v ol = 0.4 v (v dd = 3.3 v) ** in addition to those listed in table 9-4-2, cells without test pins are available. if the use of such cells is desired, contact seiko epson or its distributor. table 9-4-1 fail-safe input buffers (lv dd = 3.3 v) input level without resistor pull-down* pull-up* 50 k ? 100 k ? 50 k ? 100 k ? lvttl xlidc xlidcd1 xlidcd2 xlibbp1 xlibbp2 lvttl schmitt xlidh xlidhd1 xlidhd2 table 9-4-2 fail-safe output buffers (lv dd = 3.3 v) function i ol * cell name n-channel open-drain** tri-state normal output 2 ma xlod1t xltbf1 6 ma xlod2t xltbf2 12 ma xlod3t high speed output 2 ma xlod1ct xltbf1c 6 ma xlod2ct xltbf2c 12 ma xltbf3a
chapter 9: precautions on the use of dual power supplies 108 epson standard cell S1K50000 series design guide ? fail-safe bidirectional buffers 1) n-channel open-drain type notes * v ol = 0.4 v (lv dd = 3.3 v) ** for n-channel open-drain bidirectional buffers, in addition to those listed in table 9-4-3, the use of bidirectional buffers without test pins may be considered. if the use of such bidirectional buffers is desired, contact seiko epson or its distributor. 2) tri-state type as with tri-state output buffers, this type of cell also cannot be tied high to 5 v by adding pull-up resistors external to the standard cell. notes *1: v ol = 0.4 v (lv dd = 3.3 v), v oh = lv dd - 0.4 v (lv dd = 3.3 v) table 9-4-3 lv dd -system n-channel open-drain bidirectional buffers (lv dd = 3.3 v) input level function i ol * cell name** lvttl bi-directional output 2 ma 6 ma 12 ma xlbdc1t xlbdc2t xlbdc3t bi-directional output for high speed 2 ma 6 ma xlbdc1ct xlbdc2ct lvttl schmitt bi-directional output 2 ma 6 ma 12 ma xlbdh1t xlbdh2t xlbdh3t bi-directional output for high speed 2 ma 6 ma xlbdh1ct xlbdh2ct table 9-4-4 fail-safe cell bidirectional buffers (lv dd = 3.3 v) input level drain type test function output latch function speed output current (ma) *1 without resistor pull-down pull-up 50 k ? 100 k ? 50 k ? 100 k ? lvttl fail- safe n/a n/a normal ? / 2 xlbb1 xlbb1d1 xlbb1d2 xlbb1p1 xlbb1p2 ? / 6 xlbb2 xlbb2d1 xlbb2d2 xlbb2p1 xlbb2p2 high- speed ? / 2 xlbb1c xlbb1cd1 xlbb1cd2 xlbb1cp1 xlbb1cp2 ? / 6 xlbb2c xlbb2cd1 xlbb2cd2 xlbb2cp1 xlbb2cp2 ?2 / 12 xlbb3a xlbb3ad1 xlbb3ad2 xlbb3ap1 xlbb3ap2 lvttl schmitt fail- safe n/a n/a normal ? / 2 xlbg1 xlbg1d1 xlbg1d2 ? / 6 xlbg2 xlbg2d1 xlbg2d2 high- speed ? / 2 xlbg1c xlbg1cd1 xlbg1cd2 ? / 6 xlbg2c xlbg2cd1 xlbg2cd2 ?2 / 12 xlbg3a xlbg3ad1 xlbg3ad2 xlbg3ap1 xlbg3ap2
chapter 9: precautions on the use of dual power supplies standard cell S1K50000 series epson 109 design guide 9.3.3 hv dd -system input/output buffers the hv dd -system input/output buffers are available in several types, such as an input buffer that accepts the input of 5.0-v (or 3.3-v) signals, an output buffer that outputs 5.0-v (or 3.3-v) amplitude signals, and a bidirectional buffer that accepts the input of 5.0-v (or 3.3-v) signals and outputs 5.0-v (or 3.3-v) amplitude signals. 9.3.3.1 hv dd -system input buffers this input buffer consists only of input cells. the ?st input stage of the hv dd -system input buffer is con?ured with an hv dd -system input circuit, and the next stage is con?ured with an lv dd -system circuit. as a result, hv dd -system signals are converted into lv dd -system signals before being fed into the msi cell (internal cell area). the available types of hv dd -system input buffers are listed in tables 9-5-1 through 9-6-2. note: when ? value is 1 or 2, the pull-up/pull-down resistance values correspond to 1:60 k ? , 2:120 k ? respectively. *1 signifies the cell dedicated to hv dd of 5.0 v. table 9-5-1 hv dd -system input buffers (hv dd = 5.0 v) cell name input level fuction with or without a pull-up/down resistor xhibc xhibcp ? xhibcd ? cmos cmos cmos buffer buffer buffer without pull-up resistor (60 k ? , 120 k ? ) pull-down resistor (60 k ? , 120 k ? ) xhibt *1 xhibtp ? *1 xhibtd ? *1 ttl ttl ttl buffer buffer buffer without pull-up resistor (60 k ? , 120 k ? ) pull-down resistor (60 k ? , 120 k ? ) xhibh xhibhp ? xhibhd ? cmos schmitt cmos schmitt cmos schmitt buffer buffer buffer without pull-up resistor (60 k ? , 120 k ? ) pull-down resistor (60 k ? , 120 k ? ) xhibs *1 xhibsp ? *1 xhibsd ? *1 ttl schmitt ttl schmitt ttl schmitt buffer buffer buffer without pull-up resistor (60 k ? , 120 k ? ) pull-down resistor (60 k ? , 120 k ? ) xhibpa *1 xhibpa p ? *1 xhibpa d ? *1 pci-5v pci-5v pci-5v buffer buffer buffer without pull-up resistor (60 k ? , 120 k ? ) pull-down resistor (60 k ? , 120 k ? )
chapter 9: precautions on the use of dual power supplies 110 epson standard cell S1K50000 series design guide note: when ? value is 1 or 2, the pull-up/pull-down resistance values correspond to 1:100 k ? , 2:200 k ? respectively. note: when ? value is 1 or 2, the pull-up/pull-down resistance values correspond to 1:60 k ? , 2:120 k ? respectively. note: when ? value is 1 or 2, the pull-up/pull-down resistance values correspond to 1:100 k ? , 2:200 k ? respectively. table 9-5-2 input-level shifters (hv dd = 3.3 v) cell name input level fuction with or without a pull-up/down resistor xhibc xhibcp ? xhibcd ? lvttl lvttl lvttl buffer buffer buffer without pull-up resistor (100 k ? , 200 k ? ) pull-down resistor (100 k ? , 200 k ? ) xhibh xhibhp ? xhibhd ? lvttl schmitt lvttl schmitt lvttl schmitt buffer buffer buffer without pull-up resistor (100 k ? , 200 k ? ) pull-down resistor (100 k ? , 200 k ? ) xhibpb xhibpbp ? xhibpbd ? pci-3v pci-3v pci-3v buffer buffer buffer without pull-up resistor (100 k ? , 200 k ? ) pull-down resistor (100 k ? , 200 k ? ) table 9-6-1 input-level shifters (hv dd = 5.0 v) cell name input level fuction with or without a pull-up/down resistor xhidc xhidcd ? cmos cmos buffer buffer without pull-down resistor (60 k ? , 120 k ? ) xhidh xhidhd ? cmos schmitt cmos schmitt buffer buffer without pull-down resistor (60 k ? , 120 k ? ) table 9-6-2 input-level shifters (hv dd = 3.3 v) cell name input level fuction with or without pull-up/down resistor xhidc xhidcd ? lvttl lvttl buffer buffer without pull-down resistor (100 k ? , 200 k ? ) xhidh xhidhd ? lvttl schmitt lvttl schmitt buffer buffer without pull-down resistor (100 k ? , 200 k ? )
chapter 9: precautions on the use of dual power supplies standard cell S1K50000 series epson 111 design guide 9.3.3.2 hv dd -system output buffers the available types of S1K50000-series hv dd -system output buffers are listed in tables 9-7-1 through 9-8-2. notes * v ol = 0.4 v (hv dd = 5.0 v) ** v oh = hv dd - 0.4 v (hv dd = 5.0 v) *** for output buffers, in addition to those listed in table 9-7-1, use of a configuration without test pins may be considered. if the use of such a configuration is desired, contact seiko epson or its distributor. table 9-7-1 hv dd -system output buffers (hv dd = 5.0 v) function i ol * / i oh ** cell name*** normal output 0.1 ma / -0.1 ma 1 ma / -1 ma 3 ma / -3 ma 8 ma / -8 ma 12 ma / -12 ma 24 ma / -12 ma xhobst xhobmt xhob1t xhob2t xhob3t xhob4t output for pci pci-5v xhobpat normal output for high speed 12 ma / -12 ma 24 ma / -12 ma xhob3at xhob4at normal output for low noise 12 ma / -12 ma 24 ma / -12 ma xhob3bt xhob4bt 3-state output 0.1 ma / -0.1 ma 1 ma / -1 ma 3 ma / -3 ma 8 ma / -8 ma 12 ma / -12 ma 24 ma / -12 ma xhtbst xhtbmt xhtb1t xhtb2t xhtb3t xhtb4t output for pci pci-5v xhtbpat 3-state output for high speed 12 ma / -12 ma 24 ma / -12 ma xhtb3at xhtb4at 3-state output for low noise 12 ma / -12 ma 24 ma / -12 ma xhtb3bt xhtb4bt 3-state output (bus hold circuit) 1 ma / -1 ma 3 ma / -3 ma 8 ma / -8 ma 12 ma / -12 ma 24 ma / -12 ma xhtbmht xhtb1ht xhtb2ht xhtb3ht xhtb4ht 3-state output for high speed (bus hold circuit) 12 ma / -12 ma 24 ma / -12 ma xhtb3aht xhtb4aht 3-state output for low noise (bus hold circuit) 12 ma / -12 ma 24 ma / -12 ma xhtb3bht xhtb4bht
chapter 9: precautions on the use of dual power supplies 112 epson standard cell S1K50000 series design guide notes * v ol = 0.4 v (hv dd = 3.3 v) ** v oh = hv dd - 0.4 v (hv dd = 3.3 v) *** for output buffers, in addition to those listed in table 9-7-2, use of a configuration without test pins may be considered. if the use of such a configuration is desired, contact seiko epson or its distributor. table 9-7-2 hv dd -system output buffers (hv dd = 3.3 v) function i ol * / i oh ** cell name*** normal output 0.1 ma / -0.1 ma 1 ma / -1 ma 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xhobst xhobmt xhob1t xhob2t xhob3t output for pci pci-3v xhobpbt normal output for high speed 12 ma / -12 ma xhob3at normal output for low noise 12 ma / -12 ma xhob3bt 3-state output 0.1 ma / -0.1 ma 1 ma / -1 ma 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xhtbst xhtbmt xhtb1t xhtb2t xhtb3t output for pci pci-3v xhtbpbt 3-state output for high speed 12 ma / -12 ma xhtb3at 3-state output for low noise 12 ma / -12 ma xhtb3bt 3-state output (bus hold circuit) 1 ma / -1 ma 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xhtbmht xhtb1ht xhtb2ht xhtb3ht 3-state output for high speed (bus hold circuit) 12 ma / -12 ma xhtb3aht 3-state output for low noise (bus hold circuit) 12 ma / -12 ma xhtb3bht
chapter 9: precautions on the use of dual power supplies standard cell S1K50000 series epson 113 design guide notes * v ol = 0.4 v (hv dd = 5.0 v) ** for n-channel open-drain output buffers, in addition to those listed in table 9-8-1, use of a configuration without test pins may be considered. if the use of such a configuration is desired, contact seiko epson or its distributor. notes * v ol = 0.4 v (hv dd = 3.3 v) ** for n-channel open-drain output buffers, in addition to those listed in table 9-8-2, use of a configuration without test pins may be considered. if the use of such a configuration is desired, contact seiko epson or its distributor. table 9-8-1 hv dd -system n-channel open-drain output buffers (hv dd = 5.0 v) function i ol * cell name*** normal output 3 ma 8 ma 12 ma 24 ma xhod1t xhod2t xhod3t xhod4t table 9-8-2 hv dd -system n-channel open-drain output buffers (hv dd = 3.3 v) function i ol * cell name*** normal output 2 ma 6 ma 12 ma xhod1t xhod2t xhod3t
chapter 9: precautions on the use of dual power supplies 114 epson standard cell S1K50000 series design guide 9.3.3.3 hv dd -system bidirectional buffers the available types of S1K50000-series hv dd -system bidirectional buffers are listed in tables 9-9-1 through 9-10-2. notes * v ol = 0.4 v (hv dd = 5.0 v) ** v oh = hv dd - 0.4 v (hv dd = 5.0 v) *** for bidirectional buffers, in addition to those listed in table 9-9-1, use of bidirectional buffers configured with pull-up/pull-down resistors or without test pins may be considered. if the use of a configuration without test pins is desired, contact seiko epson or its distributor. table 9-9-1 hv dd -system bidirectional buffers (1/2) (hv dd = 5.0 v) input level function i ol * / i oh ** cell name*** ttl bi-directional output 0.1 ma / -0.1 ma 1 ma / -1 ma 3 ma / -3 ma 8 ma / -8 ma 12 ma / -12 ma 24 ma / -12 ma xhbtst xhbtmt xhbt1t xhbt2t xhbt3t xhbt4t bi-directional output for high speed 12 ma / -12 ma 24 ma / -12 ma xhbt3at xhbt4at bi-directional output for low noise 12 ma / -12 ma 24 ma / -12 ma xhbt3bt xhbt4bt cmos bi-directional output 0.1 ma / -0.1 ma 1 ma / -1 ma 3 ma / -3 ma 8 ma / -8 ma 12 ma / -12 ma 24 ma / -12 ma xhbcst xhbcmt xhbc1t xhbc2t xhbc3t xhbc4t bi-directional output for high speed 12 ma / -12 ma 24 ma / -12 ma xhbh3at xhbh4at bi-directional output for low noise 12 ma / -12 ma 24 ma / -12 ma xhbc3bt xhbc4bt pci bi-directional output for pci pci-5v xhbpat ttl schmitt bi-directional output 0.1 ma / -0.1 ma 1 ma / -1 ma 3 ma / -3 ma 8 ma / -8 ma 12 ma / -12 ma 24 ma / -12 ma xhbsst xhbsmt xhbs1t xhbs2t xhbs3t xhbs4t bi-directional output for high speed 12 ma / -12 ma 24 ma / -12 ma xhbs3at xhbs4at bi-directional output for low noise (bus hold circuit) 12 ma / -12 ma 24 ma / -12 ma xhbs3bt xhbs4bt cmos schmitt bi-directional output 0.1 ma / -0.1 ma 1 ma / -1 ma 3 ma / -3 ma 8 ma / -8 ma 12 ma / -12 ma 24 ma / -12 ma xhbhst xhbhmt xhbh1t xhbh2t xhbh3t xhbh4t bi-directional output for high speed 12 ma / -12 ma 24 ma / -12 ma xhbh3at xhbh4at bi-directional output for low noise 12 ma / -12 ma 24 ma / -12 ma xhbh3bt xhbh4bt
chapter 9: precautions on the use of dual power supplies standard cell S1K50000 series epson 115 design guide notes * v ol = 0.4 v (hv dd = 5.0 v) ** v oh = hv dd - 0.4 v (hv dd = 5.0 v) *** for bidirectional buffers, in addition to those listed in table 9-9-1, use of bidirectional buffers configured with pull-up/pull-down resistors or without test pins may be considered. if the use of a configuration without test pins is desired, contact seiko epson or its distributor. table 9-9-1 hv dd -system bidirectional buffers (2/2) (hv dd = 5.0 v) input level function i ol * / i oh ** cell name*** ttl bi-directional output (bus hold circuit) 1 ma / -1 ma 3 ma / -3 ma 8 ma / -8 ma 12 ma / -12 ma 24 ma / -12 ma xhbtmht xhbt1ht xhbt2ht xhbt3ht xhbt4ht bi-directional output for high speed (bus hold circuit) 12 ma / -12 ma 24 ma / -12 ma xhbt3aht xhbt4aht bi-directional output for low noise (bus hold circuit) 12 ma / -12 ma 24 ma / -12 ma xhbt3bht xhbt4bht cmos bi-directional output (bus hold circuit) 1 ma / -1 ma 3 ma / -3 ma 8 ma / -8 ma 12 ma / -12 ma 24 ma / -12 ma xhbcmht xhbc1ht xhbc2ht xhbc3ht xhbc4ht bi-directional output for high speed (bus hold circuit) 12 ma / -12 ma 24 ma / -12 ma xhbh3aht xhbh4aht bi-directional output for low noise (bus hold circuit) 12 ma / -12 ma 24 ma / -12 ma xhbc3bht xhbc4bht ttl schmitt bi-directional output (bus hold circuit) 1 ma / -1 ma 3 ma / -3 ma 8 ma / -8 ma 12 ma / -12 ma 24 ma / -12 ma xhbsmht xhbs1ht xhbs2ht xhbs3ht xhbs4ht bi-directional output for high speed (bus hold circuit) 12 ma / -12 ma 24 ma / -12 ma xhbs3aht xhbs4aht bi-directional output for low noise (bus hold circuit) 12 ma / -12 ma 24 ma / -12 ma xhbs3bht xhbs4bht cmos bi-directional output (bus hold circuit) 1 ma / -1 ma 3 ma / -3 ma 8 ma / -8 ma 12 ma / -12 ma 24 ma / -12 ma xhbhmht xhbh1ht xhbh2ht xhbh3ht xhbh4ht bi-directional output for high speed (bus hold circuit) 12 ma / -12 ma 24 ma / -12 ma xhbh3aht xhbh4aht bi-directional output for low noise (bus hold circuit) 12 ma / -12 ma 24 ma / -12 ma xhbh3bht xhbh4bht
chapter 9: precautions on the use of dual power supplies 116 epson standard cell S1K50000 series design guide notes * v ol = 0.4 v (hv dd = 3.3 v) ** v oh = hv dd - 0.4 v (hv dd = 3.3 v) *** for bidirectional buffers, in addition to those listed in table 9-9-2, use of bidirectional buffers configured with pull-up/pull-down resistors or without test pins may be considered. if the use of a configuration without test pins is desired, contact seiko epson or its distributor. table 9-9-2 hv dd -system bidirectional buffers (hv dd = 3.3 v) input level function i ol * / i oh ** cell name*** lvttl bi-directional output 0.1 ma / -0.1 ma 1 ma / -1 ma 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xhbcst xhbcmt xhbc1t xhbc2t xhbc3t bi-directional output for high speed 12 ma / -12 ma xhbc3at bi-directional output for low noise 12 ma / -12 ma xhbc3bt pci bi-directional output for pci pci-3v xhbpbt lvttl schmitt bi-directional output 0.1 ma / -0.1 ma 1 ma / -1 ma 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xhbhst xhbhmt xhbh1t xhbh2t xhbh3t bi-directional output for high speed 12 ma / -12 ma xhbh3at bi-directional output for low noise 12 ma / -12 ma xhbh3bt lvttl bi-directional output (bus hold circuit) 1 ma / -1 ma 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xhbcmht xhbc1ht xhbc2ht xhbc3ht bi-directional output for high speed (bus hold circuit) 12 ma / -12 ma xhbc3aht bi-directional output for low noise (bus hold circuit) 12 ma / -12 ma xhbc3bht lvttl schmitt bi-directional output (bus hold circuit) 1 ma / -1 ma 2 ma / -2 ma 6 ma / -6 ma 12 ma / -12 ma xhbhmht xhbh1ht xhbh2ht xhbh3ht bi-directional output for high speed (bus hold circuit) 12 ma / -12 ma xhbh3aht bi-directional output for low noise (bus hold circuit) 12 ma / -12 ma xhbh3bht
chapter 9: precautions on the use of dual power supplies standard cell S1K50000 series epson 117 design guide 9.3.4 hv dd -system fail-safe cells notes * v ol = 0.4 v (hv dd = 5.0 v) ** for n-channel open-drain bidirectional buffers, in addition to those listed in table 9-10-1, use of bidirectional buffers configured without test pins may be considered. if the use of a configuration without test pins is desired, contact seiko epson or its distributor. notes * v ol = 0.4 v (hv dd = 3.3 v) ** for n-channel open-drain bidirectional buffers, in addition to those listed in table 9-10-2, use of bidirectional buffers configured without test pins may be considered. if the use of a configuration without test pins is desired, contact seiko epson or its distributor. table 9-10-1 hv dd -system n-channel open-drain bidirectional buffers (hv dd = 5.0 v) input level function i ol * cell name** ttl bi-directional output 3 ma 8 ma 12 ma 24 ma xhbdt1t xhbdt2t xhbdt3t xhbdt4t cmos bi-directional output 3 ma 8 ma 12 ma 24 ma xhbdc1t xhbdc2t xhbdc3t xhbdc4t ttl schmitt bi-directional output 3 ma 8 ma 12 ma 24 ma xhbds1t xhbds2t xhbds3t xhbds4t cmos schmitt bi-directional output 3 ma 8 ma 12 ma 24 ma xhbdh1t xhbdh2t xhbdh3t xhbdh4t table 9-10-2 hv dd -system n-channel open-drain bidirectional buffers (hv dd = 3.3 v) input level function i ol * cell name** lvttl bi-directional output 2 ma 6 ma 12 ma xhbdc1t xhbdc2t xhbdc3t lvttl schmitt bi-directional output 2 ma 6 ma 12 ma xhbdh1t xhbdh2t xhbdh3t
chapter 9: precautions on the use of dual power supplies 118 epson standard cell S1K50000 series design guide 9.4 calculating the delay time in a dual-power-supply system in a dual-power-supply system, the dispersion coef?ients of delay m, listed in table 5-1, may not be used for some types of buffers, as speci?d below. the following are buffers for which the dispersion coef?ients of delay m, listed in table 5-1, cannot be used: ?hv dd -system input buffers (e.g., xhibc, xhibh) ?hv dd -system bidirectional buffers (e.g., xhbc*t, xhbh*t) for these types of buffers, the min., typ., and max values of t 0 and k are listed for your reference in the ?tandard cell S1K50000-series msi cell library. choose the appropriate t 0 and k values in accordance with the operating conditions, and use the selected values in calculation of the delay time. 1) calculating delay time (typ. value) the delay time (typ. value) in a dual-power-supply system is calculated in the same way as for a single-power-supply system. because a highly accurate delay-time calculation environment is provided, please note that the delay calculations are not in agreement with those performed using the values listed in the ?tandard cell S1K50000-series msi cell library. when calculating the delay time in input and output buffers, use the t 0 (typ.) and k (typ.) values suited for the respective operating voltages of the hv dd and lv dd -system buffers. to calculate the delay time in the internal cell (typ. value), use the t 0 (typ.) and k (typ.) values suited for the operating voltages of the lv dd -system buffers. 2) calculating the delay times (min. and max. values) and dispersion of delay coef?ients in the case of a single-power-supply system, the max. and min. values of the delay time are obtained simply by multiplying the typ. value by the coef?ient m (table 5-1). for a dual- power-supply system, on the other hand, because the dispersion coef?ient of delay differs between hv dd - and lv dd -system cells, ?st ?d the max. and min. values of the delay time in each cell. then, total the delay time of each cell thus obtained to ?d the max. and min. values of delay time in the entire circuit. however, for operation with a dual-power-supply system, the dispersion coef?ients of delay m, listed in table 5-1, cannot be used for some types of buffers such as xhibc or xhbc*t. to ?d the min. value of the delay time in such buffers, for example, use the min. values of t 0 and k available in the cell library to calculate the min. value of delay time. similarly, to ?d the max. value of the delay time, use the max. values of t 0 and k available in the cell library to calculate the max. value of the delay time.
chapter 9: precautions on the use of dual power supplies standard cell S1K50000 series epson 119 design guide 9.5 notes on calculating power consumption in a dual-power- supply system to calculate the chips power consumption in a dual-power-supply system, the power consumption must be determined separately for the hv dd - and lv dd -system cells. 1) power consumption of input buffers (pi (hv dd ) and pi (lv dd )) the calculation formula is the same as for a single-power-supply system. assuming that the power consumption of the hv dd system is represented by pi (hv dd ), and that of the lv dd system is represented by pi (lv dd ): the sum of pi (hv dd ) and pi (lv dd ) calculated from the above equations represents the power consumption of the input buffers. for the hv dd -system input buffers, use the kp i that applies to 5.0 v (or 3.3 v) and, for the lv dd system, use the kp i that applies to 3.3 v (or 2.0 v) in order to calculate the power consumption in each system. the kp i values for the respective power-supply voltages are listed in table 9-11 below. table 9-11 v dd (typ.) kp i hv dd = 5.0 v 17.7 ?/mhz hv dd (or lv dd ) = 3.3 v 6.2 ?/mhz lv dd = 2.0 v 2.0 ?/mhz p i (hv dd ) = (k p i f i ) (w) k i=1 p i (lv dd ) = (k p i f i ) (w) k i=1
chapter 9: precautions on the use of dual power supplies 120 epson standard cell S1K50000 series design guide 2) power consumption of output buffers (po (hv dd ) and po (lv dd )) the calculation formula is the same as for a single-power-supply system. assuming that the power consumption of the hv dd system is represented by po (hv dd ), and that of the lv dd system is represented by po (lv dd ): the sum of po (hv dd ) and po (lv dd ) calculated from the above equations represents the power consumption of the output buffers. be aware that the v dd value for the hv dd system differs from that for the lv dd system. note: the v oh i value differs between the hv dd and lv dd systems. 3) power consumption of internal cells (p int ) the calculation formula is the same as for a single-power-supply system. the power consumption of internal cells is obtained from the above equation. for k pint in the above equation, use the k pint that applies to lv dd . for the k pint values to use, see table 7-2. thus, the total amount of power consumption, p total , is obtained from the following equation: p total = pi (hv dd ) + pi (lv dd ) + po (hv dd ) + po (lv dd ) + p int po (hv dd ) = (p ac + p dc ) = {f i c l i (hv dd ) 2 } + {(hv dd - v oh i ) | i oh i | duty h} k i=1 k i=1 + {v ol i i ol i duty l} k i=1 po (lv dd ) = (p ac + p dc ) = {f i c l i (lv dd ) 2 } + {(lv dd - v oh i ) i oh i duty h} k i=1 k i=1 + {v ol i i ol i duty l} k i=1 p int = {(nb u) f i sp i k pint } (w) k i=1
chapter 9: precautions on the use of dual power supplies standard cell S1K50000 series epson 121 design guide 9.6 estimating the number of power-supply pins in a dual- power-supply system even during operation of a dual-power-supply system, the amount of current that can ?w through each pair of power-supply pins (for both hv dd and lv dd systems) is the same as in the case of a single-power-supply system. find the necessary number of power-supply-pin pairs separately for the hv dd and lv dd systems. * letting the current consumption in the hv dd system be i dd (hv dd ) [ma], the number of power-supply-pin pairs ni dd (hv dd ) needed for the current consumption i dd (hv dd ) is as follows: ni dd (hv dd ) i dd (hv dd ) / 50 (pair) : 50 ma per pair can be supplied * letting the current consumption in the lv dd system be i dd (lv dd ) [ma], the number of power-supply-pin pairs ni dd (lv dd ) needed for the current consumption i dd (lv dd ) is as follows: ni dd (lv dd ) i dd (lv dd ) / 50 (pair) : 50 ma per pair can be supplied when calculating the number of power-supply pins here, make sure the hv dd and lv dd systems each have at least two power-supply-pin pairs. note: if the output buffers have a dc load connected and have a steadily flowing current, one or more power-supply pins must be added. for more information, contact seiko epson or its distributor. when adding power-supply pins due to simultaneously changing outputs, do so separately for the hv dd - and lv dd -system output buffers by adding power-supply pins for each power-supply system. for the number of power-supply pins to add, see tables 8-1-1 through 8-2-2 for the 3.3-v or 2.0-v system, and tables 9-12 and 9-13 for the 5.0-v system.
chapter 9: precautions on the use of dual power supplies 122 epson standard cell S1K50000 series design guide table 9-12 number of v ss power-supply pins to add for output buffers operating simultaneously (hv dd = 5.0 v) output drive capability (i ol ) number of output buffers operating simultaneously number of power-supply pins (in pairs) to add cl 50 pf cl 100 pf cl 200 pf 8 ma 8012 16 1 2 4 24 1 3 6 32 2 4 8 12 ma 8123 16 2 3 5 24 2 5 7 32 3 6 12 24 ma & pci 8234 16 3 4 6 24 4 6 8 32 6 8 16 table 9-13 number of hv dd power-supply pins to add for output buffers operating simultaneously (hv dd = 5.0 v) output drive capability (i ol ) number of output buffers operating simultaneously number of power-supply pins (in pairs) to add cl 50 pf cl 100 pf cl 200 pf 8 ma 8011 16 1 1 3 24 1 2 4 32 1 3 5 12 ma & pci 8123 16 2 3 4 24 3 4 5 32 4 6 10
appendix: release note standard cell S1K50000 series epson 123 design guide appendix release note simulation input timing waveforms *the about timing might change with the limitation of the measuring system including a tester. a file name type waveform input pin name nrz b nrz c nrz d nrz nrz strobe * system clock strobe point rate a.p a.p a.p = active point a b c d e rate (ns) comment delay (ns) (system clock) duty
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design guide S1K50000 series first issue may, 2001 printed in ja p an c a epson electronic devices website electronic devices marketing division http://www.epsondevice.com document code: 404523701 this manual was made with recycle papaer, and printed using soy-based inks.

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